ACPI: Refactor use of global and device NVS
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig
index 9ffd7a9..d1051d8 100644
--- a/src/acpi/Kconfig
+++ b/src/acpi/Kconfig
@@ -30,9 +30,6 @@
Set to indicate <soc/nvs.h> exists for the platform with a definition
for global_nvs.
-config ACPI_HAS_DEVICE_NVS
- bool
-
config ACPI_NO_PCAT_8259
bool
help
diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl
index 1a6217a..c778376 100644
--- a/src/acpi/acpigen_extern.asl
+++ b/src/acpi/acpigen_extern.asl
@@ -9,9 +9,6 @@
#if CONFIG(ACPI_SOC_NVS)
External (GNVS, OpRegionObj)
-#endif
-
-#if CONFIG(ACPI_HAS_DEVICE_NVS)
External (DNVS, OpRegionObj)
#endif
diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
index d7fe380..8024783 100644
--- a/src/acpi/gnvs.c
+++ b/src/acpi/gnvs.c
@@ -8,32 +8,28 @@
#include <stdint.h>
#include <string.h>
#include <types.h>
-#include <vendorcode/google/chromeos/gnvs.h>
static struct global_nvs *gnvs;
+static void *dnvs;
void acpi_create_gnvs(void)
{
- size_t gnvs_size;
+ const size_t gnvs_size = ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t));
+ const size_t dnvs_size = ALIGN_UP(size_of_dnvs(), sizeof(uint64_t));
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs)
return;
- /* Match with OpRegion declared in global_nvs.asl. */
- gnvs_size = sizeof(struct global_nvs);
- if (gnvs_size < 0x100)
- gnvs_size = 0x100;
- if (CONFIG(ACPI_HAS_DEVICE_NVS))
- gnvs_size = 0x2000;
- else if (CONFIG(CHROMEOS_NVS))
- gnvs_size = 0x1000;
-
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
+ /* Allocate for both GNVS and DNVS OpRegions. */
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size + dnvs_size);
if (!gnvs)
return;
- memset(gnvs, 0, gnvs_size);
+ memset(gnvs, 0, gnvs_size + dnvs_size);
+
+ if (dnvs_size)
+ dnvs = (char *)gnvs + gnvs_size;
if (CONFIG(CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
@@ -54,19 +50,21 @@
void *acpi_get_device_nvs(void)
{
- return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+ return dnvs;
}
/* Implemented under platform. */
__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }
+__weak size_t size_of_dnvs(void) { return 0; }
/* Called from write_acpi_tables() only on normal boot path. */
void acpi_fill_gnvs(void)
{
- const struct opregion gnvs_op = OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs, 0x100);
- const struct opregion dnvs_op = OPREGION("DNVS", SYSTEMMEMORY,
- (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET, 0x1000);
+ const struct opregion gnvs_op = OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs,
+ sizeof(struct global_nvs));
+ const struct opregion dnvs_op = OPREGION("DNVS", SYSTEMMEMORY, (uintptr_t)dnvs,
+ size_of_dnvs());
if (!gnvs)
return;
@@ -76,10 +74,8 @@
acpigen_write_scope("\\");
acpigen_write_opregion(&gnvs_op);
-
- if (CONFIG(ACPI_HAS_DEVICE_NVS))
+ if (dnvs)
acpigen_write_opregion(&dnvs_op);
-
acpigen_pop_len();
}
diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h
index 976726a..ef98b66 100644
--- a/src/include/acpi/acpi_gnvs.h
+++ b/src/include/acpi/acpi_gnvs.h
@@ -8,6 +8,8 @@
struct global_nvs;
void acpi_create_gnvs(void);
+size_t size_of_dnvs(void);
+
#if CONFIG(ACPI_SOC_NVS)
void *acpi_get_gnvs(void);
void *acpi_get_device_nvs(void);
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index a9ba092..9af65ee 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -8,7 +8,6 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
- select ACPI_HAS_DEVICE_NVS
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 0b681b0..26e0b6e 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -13,6 +13,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <soc/device_nvs.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/msr.h>
@@ -116,6 +117,11 @@
attrs->bclk_khz = bus_freq_khz();
}
+size_t size_of_dnvs(void)
+{
+ return sizeof(struct device_nvs);
+}
+
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps)
{
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index e48ddba..20e1590 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -20,8 +20,6 @@
#include <soc/nvs.h>
#include <soc/device_nvs.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
@@ -210,7 +208,7 @@
void *acpi_get_device_nvs(void)
{
- return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+ return (u8 *)gnvs + ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t));
}
/*
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index f91e7de..9a55672 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -8,7 +8,6 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
- select ACPI_HAS_DEVICE_NVS
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 2d7ca3c..c70b69d 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -13,6 +13,7 @@
#include <device/pci.h>
#include <drivers/intel/gma/opregion.h>
#include <soc/acpi.h>
+#include <soc/device_nvs.h>
#include <soc/gfx.h>
#include <soc/iomap.h>
#include <soc/irq.h>
@@ -60,6 +61,11 @@
}
};
+size_t size_of_dnvs(void)
+{
+ return sizeof(struct device_nvs);
+}
+
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* Fill in the Wi-Fi Region ID */
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index f6dcaea..a25b2b0 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -8,8 +8,6 @@
#define ACTIVE_ECFW_RO 0
#define ACTIVE_ECFW_RW 1
-#define GNVS_DEVICE_NVS_OFFSET 0x1000
-
struct chromeos_acpi {
/* ChromeOS specific */
u32 vbt0; // 00 boot reason