tree 6e9556d8cb08657dda909bf2228e6f4cd815fa83
parent d5ae3f908af3c5201bd42fe411b32f97ac35ea4d
author Cliff Huang <cliff.huang@intel.com> 1642753395 -0800
committer Felix Held <felix-coreboot@felixheld.de> 1644243014 +0000

soc/intel/common/block/pcie/rtd3: Add PM methods to the device.

Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.

Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>