tree dbc2920ae531a31a7da5f88ca245662f592e8de8
parent 34aa639a2678ab8675c03e8d64d73b82f04cdad4
author Jamie Ryu <jamie.m.ryu@intel.com> 1659456863 -0700
committer Martin Roth <martin.roth@amd.corp-partner.google.com> 1661356754 +0000

soc/intel/common/gpio: Support 4 bits GPIO pad mode configuration

Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins
that native function 8 to 15 is assigned. This adds native function
definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support
4 bits pad mode configuration.

Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not
assigned, this change would not cause an issue but Kconfig option is
added to minimize an impact and support 4 bits pad mode configuration.

BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>