tree 9a085ecbfd024dfa297850d125773f72d71c95fc
parent 9baffae485a7008ddc232b90126fe43615d61269
author Shelley Chen <shchen@google.com> 1664238460 -0700
committer Shelley Chen <shchen@google.com> 1665075348 +0000

soc/qualcomm: Update the wait time for checking PCIe link up

Currently, after the PCIe link is initialized, we wait 100ms every
time the link is not up anymore.  However, this causes significant
delay.  Assuming the first check is false, we'd like to increase the
frequency of checks for the link to be up.  Changing to check every
10ms instead.  This seems to save about 90ms in the device
configuration stage of bootup on herobrine.

BUG=b:218406702
BRANCH=None
TEST=reboot from AP console (on herobrine)
     prior to fix (from cbmem dump):
         40:device configuration 919,391 (202,861)
     after fix (from cbmem dump):
         40:device configuration 826,294 (112,729)

Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: mturney mturney <quic_mturney@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>