tree f413f852122f395bc70793572956a80b5e8cbf9b
parent 344a1bd43c63dbfeb3cff04e63d531f32242aba4
author Angel Pons <th3fanbus@gmail.com> 1604075776 +0100
committer Angel Pons <th3fanbus@gmail.com> 1604758700 +0000

sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

For all these southbridges, the lower nibble of PCICMD is read-only.

Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.

Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>