arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
diff --git a/src/arch/x86/include/arch/hpet.h b/src/arch/x86/include/arch/hpet.h
new file mode 100644
index 0000000..224279e
--- /dev/null
+++ b/src/arch/x86/include/arch/hpet.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ARCH_X86_HPET_H
+#define ARCH_X86_HPET_H
+
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#endif /* ARCH_X86_HPET_H */
diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c
index 97cff28..f62532c 100644
--- a/src/soc/amd/cezanne/data_fabric.c
+++ b/src/soc/amd/cezanne/data_fabric.c
@@ -2,6 +2,7 @@
#include <acpi/acpi_device.h>
#include <amdblocks/data_fabric.h>
+#include <arch/hpet.h>
#include <console/console.h>
#include <cpu/x86/lapic_def.h>
#include <device/device.h>
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 490e27c..a6efce7 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -15,7 +15,7 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#define HPET_BASE_ADDRESS 0xfed00000
+#include <arch/hpet.h> /* This will be removed in a follow-up patch */
#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
#error HPET address must be 0xfed00000
#endif
diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c
index f8204ff..75d72e9 100644
--- a/src/soc/amd/picasso/data_fabric.c
+++ b/src/soc/amd/picasso/data_fabric.c
@@ -2,6 +2,7 @@
#include <acpi/acpi_device.h>
#include <amdblocks/data_fabric.h>
+#include <arch/hpet.h>
#include <console/console.h>
#include <cpu/x86/lapic_def.h>
#include <device/device.h>
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 2d6999d..1ce581e 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -10,7 +10,7 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#define HPET_BASE_ADDRESS 0xfed00000
+#include <arch/hpet.h> /* This will be removed in a follow-up patch */
#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
#error HPET address must be 0xfed00000
#endif
diff --git a/src/soc/amd/sabrina/data_fabric.c b/src/soc/amd/sabrina/data_fabric.c
index 0ba5c87..8f821c3 100644
--- a/src/soc/amd/sabrina/data_fabric.c
+++ b/src/soc/amd/sabrina/data_fabric.c
@@ -4,6 +4,7 @@
#include <acpi/acpi_device.h>
#include <amdblocks/data_fabric.h>
+#include <arch/hpet.h>
#include <console/console.h>
#include <cpu/x86/lapic_def.h>
#include <device/device.h>
diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h
index 9854986..cfe4184 100644
--- a/src/soc/amd/sabrina/include/soc/iomap.h
+++ b/src/soc/amd/sabrina/include/soc/iomap.h
@@ -15,7 +15,7 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#define HPET_BASE_ADDRESS 0xfed00000
+#include <arch/hpet.h> /* This will be removed in a follow-up patch */
#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
#error HPET address must be 0xfed00000
#endif
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index a678bb2..75c0973 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -16,7 +16,7 @@
#define APU_I2C2_BASE 0xfedc4000
#define APU_I2C3_BASE 0xfedc5000
-#define HPET_BASE_ADDRESS 0xfed00000
+#include <arch/hpet.h> /* This will be removed in a follow-up patch */
#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
#error HPET address must be 0xfed00000
#endif
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 5d5ed7a..04472dc 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -4,6 +4,7 @@
#include <amdblocks/biosram.h>
#include <amdblocks/hda.h>
#include <device/pci_ops.h>
+#include <arch/hpet.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index fc8552c..0941b0e 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 23b7c5b..9ff8f54 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -59,8 +59,6 @@
#define REG_BASE_ADDRESS 0xfb000000
#define REG_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index e92227b..209e1c2 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -10,8 +10,6 @@
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE (32 * KiB)
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define ACPI_BASE_ADDRESS 0x400
#define ACPI_BASE_SIZE 0x100
#define R_ACPI_PM1_TMR 0x8
diff --git a/src/soc/intel/baytrail/include/soc/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h
index b5bea50..c11a20a 100644
--- a/src/soc/intel/baytrail/include/soc/iomap.h
+++ b/src/soc/intel/baytrail/include/soc/iomap.h
@@ -42,9 +42,6 @@
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x400
-/* High Performance Event Timer */
-#define HPET_BASE_ADDRESS 0xfed00000
-
/* Temporary Base Address */
#define TEMP_BASE_ADDRESS 0xfd000000
diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h
index 65fe4ac..9220f69 100644
--- a/src/soc/intel/braswell/include/soc/iomap.h
+++ b/src/soc/intel/braswell/include/soc/iomap.h
@@ -43,9 +43,6 @@
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x400
-/* High Performance Event Timer */
-#define HPET_BASE_ADDRESS 0xfed00000
-
/* Temporary Base Address */
#define TEMP_BASE_ADDRESS 0xfd000000
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h
index 0f9f38f..551f659 100644
--- a/src/soc/intel/broadwell/include/soc/iomap.h
+++ b/src/soc/intel/broadwell/include/soc/iomap.h
@@ -5,8 +5,6 @@
#include <northbridge/intel/haswell/memmap.h>
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define ACPI_BASE_ADDRESS 0x1000
#define ACPI_BASE_SIZE 0x100
diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c
index 2f76111..80c7721 100644
--- a/src/soc/intel/broadwell/pch/bootblock.c
+++ b/src/soc/intel/broadwell/pch/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <arch/hpet.h>
#include <device/pci_ops.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index e09cec2..a714952 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -39,8 +39,6 @@
#define REG_BASE_ADDRESS 0xfc000000
#define REG_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl
index 6c75a47..c4a7dd3 100644
--- a/src/soc/intel/common/block/acpi/acpi/lpc.asl
+++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel LPC/eSPI Bus Device - 0:1f.0 */
+#include <arch/hpet.h>
#include <soc/iomap.h>
Device (LPCB)
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 89495a9..be14d18 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <arch/hpet.h>
#include <soc/iomap.h>
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
index ca14719..827444a 100644
--- a/src/soc/intel/denverton_ns/include/soc/iomap.h
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -16,8 +16,6 @@
#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
#define DEFAULT_TCO_BASE 0x400
-#define HPET_BASE_ADDRESS 0xfed00000
-
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_PCR_BASE 0xfd000000
#define DEFAULT_PWRM_BASE 0xfe000000
diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h
index dbbd229..0e36c9f 100644
--- a/src/soc/intel/elkhartlake/include/soc/iomap.h
+++ b/src/soc/intel/elkhartlake/include/soc/iomap.h
@@ -30,8 +30,6 @@
#define REG_BASE_ADDRESS 0xfb000000
#define REG_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h
index cee9411..becb045 100644
--- a/src/soc/intel/icelake/include/soc/iomap.h
+++ b/src/soc/intel/icelake/include/soc/iomap.h
@@ -30,8 +30,6 @@
#define REG_BASE_ADDRESS 0xfc000000
#define REG_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h
index a6ac836..88ccdcf 100644
--- a/src/soc/intel/jasperlake/include/soc/iomap.h
+++ b/src/soc/intel/jasperlake/include/soc/iomap.h
@@ -41,8 +41,6 @@
#define REG_BASE_ADDRESS 0xfb000000
#define REG_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 709e1f7..36d4932 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <soc/iomap.h>
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index d3fb957..9245f4b 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -35,8 +35,6 @@
#define VTVC0_BASE_ADDRESS 0xfed91000
#define VTVC0_BASE_SIZE 0x1000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index dec1950..51f637a 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -59,8 +59,6 @@
#define REG_BASE_ADDRESS 0xfb000000
#define REG_BASE_SIZE 0x4000
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h
index ceaf271..5daf62b 100644
--- a/src/soc/intel/xeon_sp/include/soc/iomap.h
+++ b/src/soc/intel/xeon_sp/include/soc/iomap.h
@@ -26,9 +26,6 @@
#define VGA_BASE_ADDRESS 0xa0000
#define VGA_BASE_SIZE 0x20000
-/* High Performance Event Timer */
-#define HPET_BASE_ADDRESS 0xfed00000
-
#define HECI1_BASE_ADDRESS 0xfed1a000
#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index bb98f0b..0519d44 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpigen.h>
+#include <arch/hpet.h>
#include <assert.h>
#include <cbmem.h>
#include <device/mmio.h>
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 8d1139d..f1ac4c9 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h> /* Include this before OEM.h to have HPET_BASE_ADDRESS from arch/x86 */
#include "SBPLATFORM.h"
#include "cfg.h"
#include <OEM.h>