commonlib/lz4: Avoid unaligned memory access on RISC-V

From the User-Level ISA Specification v2.0:

   "We do not mandate atomicity for misaligned accesses so simple
    implementations can just use a machine trap and software handler to
    handle misaligned accesses." (— http://riscv.org/specifications/)

Spike traps on unaligned accesses.

Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index 772f791..93fa7e8 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -63,6 +63,11 @@
 			: [src]"r"(src), [dst]"r"(dst)
 			: "memory" );
 	#endif
+#elif defined(__riscv__)
+	/* RISC-V implementations may trap on any unaligned access. */
+	int i;
+	for (i = 0; i < 8; i++)
+		((uint8_t *)dst)[i] = ((uint8_t *)src)[i];
 #else
 	*(uint64_t *)dst = *(const uint64_t *)src;
 #endif