i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.
For compatibility with old bootblocks also enable it early in romstage.
Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 39a8e46..443fdc5 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -216,9 +216,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 7b60ae5..b57e6b7 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -191,9 +191,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 38e8620..ece65d8 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -163,9 +163,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 4508968..4194a80 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -89,9 +89,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index dc7da99..652d8cb 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -222,9 +222,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Now, this is a bit ugly. As per PCI specification, function 0 of a
* device always has to be implemented. So disabling ethernet port 1
* would essentially disable all three ethernet ports of the mainboard.
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 350c2de..571a21c 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -137,9 +137,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 4596a1a..af9b1be 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -144,9 +144,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index c9ec4f1..e8ada36 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -169,9 +169,6 @@
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 08ffdf6..b12ad3a 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -171,6 +171,9 @@
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 7b4cd7d..d8e03b7 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
+#include "i82801gx.h"
static void store_initial_timestamp(void)
{
@@ -50,4 +51,10 @@
store_initial_timestamp();
#endif
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
}