commit | 18d315910adddec70d69fc1cc97426e5bbe9dd5a | [log] [tgz] |
---|---|---|
author | Christian Walter <christian.walter@9elements.com> | Tue Jul 07 16:57:15 2020 +0200 |
committer | Patrick Georgi <pgeorgi@google.com> | Sun Jul 12 19:40:19 2020 +0000 |
tree | 40382e6710d799abe1ca3aa1029557f16f807003 | |
parent | 07ac2ec021cf504679f55a7365332e6dc7da0cd6 [diff] |
soc/intel/common/block/pcie: Select ASPM on mainboard basis Current the common soc code automatically selects PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA graphics card attached on mainboards that do not have a CLKREQ# signal. This is commonly used on server and workstations boards where the additional power savings of L1 substate are not required. Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not select it anymore by the soc code, thus we can disable it in the mainboard code. Tested on CFL with Windows 10. Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.