soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and
performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later
in the boot process to ensure that the memory training parameters are
written back to SPI flash before performing a reset for CSE RW
jump. With the recent changes in CB:44196 ("mrc_cache: Update
mrc_cache data in romstage"), MRC cache is updated right away in
romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I947a40cd9776342d2067c9d5a366358917466d58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 9c498b5..9011593 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -809,12 +809,4 @@
}
}
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
-/*
- * This needs to happen after the MRC cache write to avoid a 2nd
- * memory training sequence.
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL);
-#else
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
-#endif