diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl
index c43d2db..aecc2b6 100644
--- a/src/mainboard/intel/littleplains/acpi/mainboard.asl
+++ b/src/mainboard/intel/littleplains/acpi/mainboard.asl
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
+// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
+
 Device (PWRB)
 {
 	Name(_HID, EisaId("PNP0C0C"))
diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl
index dbb8b15..ec56e26 100644
--- a/src/mainboard/intel/littleplains/dsdt.asl
+++ b/src/mainboard/intel/littleplains/dsdt.asl
@@ -23,6 +23,9 @@
 	0x20110725	// OEM revision
 )
 {
+	// Include mainboard configuration
+	#include <acpi/mainboard.asl>
+
 	// Include debug methods
 	#include <arch/x86/acpi/debug.asl>
 
diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
index c43d2db..aecc2b6 100644
--- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
+++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
+// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
+
 Device (PWRB)
 {
 	Name(_HID, EisaId("PNP0C0C"))
diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl
index dbb8b15..ec56e26 100644
--- a/src/mainboard/intel/mohonpeak/dsdt.asl
+++ b/src/mainboard/intel/mohonpeak/dsdt.asl
@@ -23,6 +23,9 @@
 	0x20110725	// OEM revision
 )
 {
+	// Include mainboard configuration
+	#include <acpi/mainboard.asl>
+
 	// Include debug methods
 	#include <arch/x86/acpi/debug.asl>
 
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index 22edf50..696a81a 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -30,7 +30,7 @@
 		TRP0, 8		// IO-Trap at 0x808
 	}
 
-#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO)
+#ifdef ACPI_INCLUDE_PMIO
 	// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
 	OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80)
 	Field(PMIO, ByteAcc, NoLock, Preserve)
@@ -77,7 +77,7 @@
 	}
 #endif
 
-#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO)
+#ifdef ACPI_INCLUDE_GPIO
 	// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
 	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
 	Field(GPIO, ByteAcc, NoLock, Preserve)