Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.

This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>                                                                                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 2d7936b..3817161 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -9,6 +9,7 @@
 romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
+romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@@ -29,6 +30,7 @@
 ramstage-y += clog2.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
+ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 
@@ -36,5 +38,6 @@
 
 smm-y += memcpy.c
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
+smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 
 $(obj)/lib/version.ramstage.o : $(obj)/build.h