soc/apollolake: Add ish_enable in soc_intel_apollolake_config
Also initialize IshEnable in Silicon Init UPD with the value from
devicetree.cb
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d
Reviewed-on: https://review.coreboot.org/14894
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f2..610faa8 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -120,6 +120,8 @@
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR;
+
+ silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
}
struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index d74084e..3d9f5bd 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -42,6 +42,9 @@
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
+
+ /* Integrated Sensor Hub */
+ uint8_t integrated_sensor_hub_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */