tree b2d803e763448acfd09c863fad20d08bc241b24f
parent c5c35ce238e2ce032db7bc5e0addba1c2d46ef53
author Arthur Heymans <arthur@aheymans.xyz> 1689250074 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1695918655 +0000

soc/amd/genoa: Add timer & tsc support

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>