soc/amd/genoa: Add timer & tsc support
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 7ef5707..b73b53c 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -8,13 +8,13 @@
select ARCH_X86
select HAVE_EXP_X86_64_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
- select NO_MONOTONIC_TIMER
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
- select UNKNOWN_TSC_RATE
+ select SOC_AMD_COMMON_BLOCK_TSC
select X86_CUSTOM_BOOTMEDIA
config USE_EXP_X86_64_SUPPORT
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 0e08ac6..56a98e6 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -9,7 +9,6 @@
romstage-y += romstage.c
ramstage-y += chip.c
-ramstage-y += timer.c
CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
diff --git a/src/soc/amd/genoa/include/soc/msr.h b/src/soc/amd/genoa/include/soc/msr.h
new file mode 100644
index 0000000..368c631
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/msr.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_MSR_H
+#define AMD_GENOA_MSR_H
+
+/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
+union pstate_msr {
+ struct {
+ uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */
+ uint64_t cpu_dfs_id : 6; /* [ 8..13] */
+ uint64_t cpu_vid_0_7 : 8; /* [14..21] */
+ uint64_t idd_value : 8; /* [22..29] */
+ uint64_t idd_div : 2; /* [30..31] */
+ uint64_t cpu_vid_8 : 1; /* [32..32] */
+ uint64_t : 30; /* [33..62] */
+ uint64_t pstate_en : 1; /* [63..63] */
+ };
+ uint64_t raw;
+};
+
+
+/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
+#define MSR_CPPC_CAPABILITY_1 0xc00102b0
+#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
+#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16
+#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8
+#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0
+
+#define MSR_CPPC_ENABLE 0xc00102b1
+#define MSR_CPPC_REQUEST 0xc00102b3
+#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24
+#define SHIFT_CPPC_REQUEST_DES_PERF 16
+#define SHIFT_CPPC_REQUEST_MIN_PERF 8
+#define SHIFT_CPPC_REQUEST_MAX_PERF 0
+
+#define MSR_CPPC_STATUS 0xc00102b4
+
+#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7
+#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8
+
+#endif /* AMD_GENOA_MSR_H */
diff --git a/src/soc/amd/genoa/timer.c b/src/soc/amd/genoa/timer.c
deleted file mode 100644
index 9054ffd..0000000
--- a/src/soc/amd/genoa/timer.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <delay.h>
-
-void init_timer(void)
-{
-}