tree bb9cfd0dbd9d2e14d30dfc10bb90a8307760662a
parent 719d85bf569697a489a6ba7416870f4ec6d5b086
author Lean Sheng Tan <lean.sheng.tan@intel.com> 1626685036 -0700
committer Werner Zeh <werner.zeh@siemens.com> 1627535928 +0000

soc/intel/elkhartlake: Update UART clock divider params

As EHL UART source clock is 120MHz, update the clock divider
parameters (M & N) to reflect the right value.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>