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/*
* This file is part of the coreboot project.
*
* Copyright (c) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_CANNONLAKE_PCR_H
#define SOC_CANNONLAKE_PCR_H
/*
* Port ids
*/
#define PID_GPIOCOM4 0x6a
#define PID_GPIOCOM3 0x6b
#define PID_GPIOCOM2 0x6c
#define PID_GPIOCOM1 0x6d
#define PID_GPIOCOM0 0x6e
#define PID_DMI 0x88
#define PID_PSTH 0x89
#define PID_PSF1 0xba
#define PID_PSF2 0xbb
#define PID_PSF3 0xbc
#define PID_PSF4 0xbd
#define PID_SCS 0xc0
#define PID_RTC 0xc3
#define PID_ITSS 0xc2
#define PID_LPC 0xc7
#define PID_SERIALIO 0xcb
#endif