commit 467802b6285b2b9a76f755dffeef61194ee35373
author Wim Vervoorn <wvervoorn@eltan.com> Thu Oct 17 13:20:42 2019 +0200
committer Patrick Georgi <pgeorgi@google.com> Fri Oct 18 12:27:12 2019 +0000
tree dfbaa46da2dadd63d625ebdd2d0fe0dfe55be438
parent bac6946956ac2b801b9895f7443dca055a639d64

mb/facebook/fbg1701: separate cpld support

Move all code involving the cpld to a single file.
Rename mainboard_read_pcb_version() to cpld_read_pcb_version().

BUG=N/A
TEST=tested on fbg1701 board

Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/facebook/fbg1701/ramstage.c

diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c
index 980a6cc..e2b4ac3 100644
--- a/src/mainboard/facebook/fbg1701/ramstage.c
+++ b/src/mainboard/facebook/fbg1701/ramstage.c
@@ -19,7 +19,7 @@
 #include <soc/ramstage.h>
 #include <soc/smbus.h>
 #include "mainboard.h"
-#include "onboard.h"
+#include "cpld.h"
 
 struct edp_data {
 	u8 payload_length;
@@ -326,16 +326,19 @@
 {
 	const struct edp_data *edptable;
 	unsigned int loops;
+	unsigned int pcb_version;
 	int status;
 
-	if (mainboard_read_pcb_version() < 7)
+	pcb_version = cpld_read_pcb_version();
+	printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version);
+
+	if (pcb_version < 7)
 		edptable = b101uan01_table;
 	else
 		edptable = b101uan08_table;
 
 	/* reset bridge */
-	outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT);
-	outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT);
+	cpld_reset_bridge();
 
 	while (edptable->payload_length) {
 		loops = 5;