Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
diff --git a/src/Kconfig b/src/Kconfig
index f538a1c..3742c04 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -354,6 +354,21 @@
Skip PCI enumeration logic and only allocate BAR for fixed devices
(bootable devices, TPM over GSPI).
+config CONFIGURABLE_RAMSTAGE
+ bool "Enable a configurable ramstage."
+ default y if ARCH_X86
+ help
+ A configurable ramstage allows you to select which parts of the ramstage
+ to run. Currently, we can only select a minimal PCI scanning step.
+ The minimal PCI scanning will only check those parts that are enabled
+ in the devicetree.cb. By convention none of those devices should be bridges.
+
+config MINIMAL_PCI_SCANNING
+ bool "Enable minimal PCI scanning"
+ depends on CONFIGURABLE_RAMSTAGE
+ help
+ If this option is enabled, coreboot will scan only devices
+ marked as mandatory in devicetree.cb
endmenu
menu "Mainboard"
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 47c0e9f..b1e88a6 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1195,6 +1195,12 @@
* non-existence and single function devices.
*/
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
+ if (CONFIG(MINIMAL_PCI_SCANNING)) {
+ dev = pcidev_path_behind(bus, devfn);
+ if (!dev || !dev->mandatory)
+ continue;
+ }
+
/* First thing setup the device structure. */
dev = pci_scan_get_dev(bus, devfn);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index c3a1106..333ac5d 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -119,7 +119,10 @@
unsigned int initialized : 1; /* 1 if we have initialized the device */
unsigned int on_mainboard : 1;
unsigned int disable_pcie_aspm : 1;
- unsigned int hidden : 1; /* set if we should hide from UI */
+ /* set if we should hide from UI */
+ unsigned int hidden : 1;
+ /* set if this device is used even in minimum PCI cases */
+ unsigned int mandatory : 1;
u8 command;
uint16_t hotplug_buses; /* Number of hotplug buses to allocate */
diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb
index 671a2d6..c032606 100644
--- a/src/mainboard/emulation/qemu-q35/devicetree.cb
+++ b/src/mainboard/emulation/qemu-q35/devicetree.cb
@@ -5,10 +5,10 @@
end
end
device domain 0 on
- device pci 0.0 on end # northbridge (q35)
+ device pci 0.0 mandatory end # northbridge (q35)
chip southbridge/intel/i82801ix
# present unconditionally
- device pci 1f.0 on end # LPC
+ device pci 1f.0 mandatory end # LPC
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus