mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbi
copy from dibbi since taranza base on dibbi,this is only for first
initial configuration, will update the more setting afterward.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index cfb4186..10cf5e2 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -205,6 +205,9 @@
config BOARD_GOOGLE_TARANZA
bool "-> Taranza"
select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
+ select RT8168_GEN_ACPI_POWER_RESOURCE
+ select RT8168_GET_MAC_FROM_VPD
+ select RT8168_SET_LED_MODE
config BOARD_GOOGLE_BOXY
bool "-> Boxy"
diff --git a/src/mainboard/google/dedede/variants/taranza/Makefile.inc b/src/mainboard/google/dedede/variants/taranza/Makefile.inc
new file mode 100644
index 0000000..eb2c9bc
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/taranza/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/dedede/variants/taranza/gpio.c b/src/mainboard/google/dedede/variants/taranza/gpio.c
new file mode 100644
index 0000000..89a7a77
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/taranza/gpio.c
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+ /* A11 : TOUCH_RPT_EN */
+ PAD_NC(GPP_A11, NONE),
+ /* A12 : USB_OC1_N */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A13 : USB_OC2_N */
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+ /* A14 : USB_OC3_N */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+ /* A18 : USB_OC0_N */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+ /* B9 : LAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+
+ /* D2 : PWM_PP3300_BUZZER */
+ PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ /* D4 : LAN_PE_ISOLATE_ODL_R */
+ PAD_CFG_GPO(GPP_D4, 1, DEEP),
+ /* D5 : TOUCH_RESET_L */
+ PAD_NC(GPP_D5, NONE),
+ /* D6 : EN_PP3300_TOUCH_S0 */
+ PAD_NC(GPP_D6, NONE),
+ /* D17 : LAN_PERST_L */
+ PAD_CFG_GPO(GPP_D17, 1, PLTRST),
+ /* D19 : WWAN_WLAN_COEX1 */
+ PAD_NC(GPP_D19, NONE),
+ /* D20 : WWAN_WLAN_COEX2 */
+ PAD_NC(GPP_D20, NONE),
+
+ /* E13 : GPP_E13/DDI0_DDC_SCL */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+ /* E14 : GPP_E14/DDI0_DDC_SDA */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* E15 : GPP_E15/DDI1_DDC_SCL */
+ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+ /* E16 : GPP_E16/DDI1_DDC_SDA */
+ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+ /* G0 : SD_CMD */
+ PAD_NC(GPP_G0, NONE),
+ /* G1 : SD_DATA0 */
+ PAD_NC(GPP_G1, NONE),
+ /* G2 : SD_DATA1 */
+ PAD_NC(GPP_G2, NONE),
+ /* G3 : SD_DATA2 */
+ PAD_NC(GPP_G3, NONE),
+ /* G4 : SD_DATA3 */
+ PAD_NC(GPP_G4, NONE),
+ /* G5 : SD_CD_ODL */
+ PAD_NC(GPP_G5, NONE),
+ /* G6 : SD_CLK */
+ PAD_NC(GPP_G6, NONE),
+ /* G7 : SD_SDIO_WP */
+ PAD_NC(GPP_G7, NONE),
+
+ /* H4 : AP_I2C_TS_SDA */
+ PAD_NC(GPP_H4, NONE),
+ /* H5 : AP_I2C_TS_SCL */
+ PAD_NC(GPP_H5, NONE),
+ /* H6 : AP_I2C_CAM_SDA */
+ PAD_NC(GPP_H6, NONE),
+ /* H7 : AP_I2C_CAM_SCL */
+ PAD_NC(GPP_H7, NONE),
+ /* H15 : I2S_SPK_BCLK */
+ PAD_NC(GPP_H15, NONE),
+
+ /* R6 : I2S_SPK_LRCK */
+ PAD_NC(GPP_R6, NONE),
+ /* R7 : I2S_SPK_AUDIO */
+ PAD_NC(GPP_R7, NONE),
+
+ /* S2 : DMIC1_CLK */
+ PAD_NC(GPP_S2, NONE),
+ /* S3 : DMIC1_DATA */
+ PAD_NC(GPP_S3, NONE),
+ /* S6 : DMIC0_CLK */
+ PAD_NC(GPP_S6, NONE),
+ /* S7 : DMIC0_DATA */
+ PAD_NC(GPP_S7, NONE),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index 404024b..e3df1f2 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -8,10 +8,6 @@
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
- #| I2C0 | Trackpad |
- #| I2C1 | Digitizer |
- #| I2C2 | Touchscreen |
- #| I2C3 | Camera |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
@@ -19,24 +15,245 @@
.speed_mhz = 1,
.early_init = 1,
},
- .i2c[0] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[1] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[2] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[3] = {
- .speed = I2C_SPEED_FAST,
- },
.i2c[4] = {
- .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 40,
+ }
},
}"
+ # Enable Root Port 3 (index 2) for LAN
+ # External PCIe port 7 is mapped to PCIe Root Port 3
+ register "PcieRpEnable[2]" = "1"
+ register "PcieClkSrcUsage[4]" = "2"
+
+ # Enable Root Port 7 (index 6) for WLAN
+ # External PCIe port 3 is mapped to PCIe Root Port 7
+ register "PcieRpEnable[6]" = "1"
+ register "PcieClkSrcUsage[3]" = "6"
+
+ # Disable PCIe Root Port 8
+ register "PcieRpEnable[7]" = "0"
+
+ # Audio related configurations
+ register "PchHdaAudioLinkDmicEnable[0]" = "0"
+ register "PchHdaAudioLinkDmicEnable[1]" = "0"
+
+ # Disable SD card
+ register "sdcard_cd_gpio" = "0"
+ register "SdCardPowerEnableActiveHigh" = "0"
+
+ # Disable eDP on port A
+ register "DdiPortAConfig" = "0"
+
+ # Enable HPD and DDC for DDI port A
+ register "DdiPortAHpd" = "1"
+ register "DdiPortADdc" = "1"
+
+ # USB Port Configuration
+ register "usb2_ports[0]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_11P25MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-C Port 0
+ register "usb2_ports[1]" = "{
+ .enable = 1,
+ .ocpin = OC1,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_11P25MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port A0
+ register "usb2_ports[2]" = "{
+ .enable = 1,
+ .ocpin = OC2,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_11P25MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port A1
+ register "usb2_ports[3]" = "{
+ .enable = 1,
+ .ocpin = OC3,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_11P25MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port A2
+ register "usb2_ports[4]" = "{
+ .enable = 1,
+ .ocpin = OC0,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_11P25MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port A3
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # PL2303
+
+ register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
+
device domain 0 on
- device pci 15.0 on end
+ device pci 04.0 on
+ chip drivers/intel/dptf
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
+ }"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
+ }"
+
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 3000,
+ .max_power = 6000,
+ .time_window_min = 1 * MSECS_PER_SEC,
+ .time_window_max = 1 * MSECS_PER_SEC,
+ .granularity = 100,
+ },
+ .pl2 = {
+ .min_power = 20000,
+ .max_power = 20000,
+ .time_window_min = 1 * MSECS_PER_SEC,
+ .time_window_max = 1 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ register "options.tsr[0].desc" = ""Memory""
+ register "options.tsr[1].desc" = ""Power""
+ register "options.tsr[2].desc" = ""Chassis""
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 3000 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ device generic 0 on end
+ end
+ end # SA Thermal device
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ # TODO (b/264960828) verify PLD values
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A1""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 3)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A2""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 4)"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A3""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 5)"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ device usb 3.1 off end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A1""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 3)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A2""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 4)"
+ device usb 3.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A3""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 5)"
+ device usb 3.5 on end
+ end
+ end
+ end
+ end # USB xHCI
+ device pci 15.0 off end # I2C 0
+ device pci 15.1 off end # I2C 1
+ device pci 15.2 off end # I2C 2
+ device pci 15.3 off end # I2C 3
+ device pci 19.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""RTL5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end # I2C 4
+ device pci 1c.2 on
+ chip drivers/net
+ register "customized_leds" = "0x05af"
+ register "wake" = "GPE0_DW0_03" # GPP_B3
+ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ register "device_index" = "0"
+ device pci 00.0 on end
+ end
+ end # PCI Express Root Port 3 - RTL8111H LAN
+ device pci 1c.6 on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_DW2_03"
+ device pci 00.0 on end
+ end
+ end # PCI Express Root Port 7 - WLAN
+ device pci 1c.7 off end # PCI Express Root Port 8
+ device pci 1f.3 on end # Intel HDA
end
end