mb/google/myst: Enable PCIe devices in devicetree
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c
index 9d3b15b..703b74b 100644
--- a/src/mainboard/google/myst/port_descriptors.c
+++ b/src/mainboard/google/myst/port_descriptors.c
@@ -1,11 +1,92 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <baseboard/variants.h>
+#include <gpio.h>
#include <soc/platform_descriptors.h>
#include <types.h>
+static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
+ { /* WWAN */
+ .engine_type = UNUSED_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 13,
+ .end_logical_lane = 13,
+ .device_number = PCI_SLOT(WWAN_DEVFN),
+ .function_number = PCI_FUNC(WWAN_DEVFN),
+ .link_speed_capability = GEN3,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ2,
+ },
+ { /* WLAN */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 14,
+ .end_logical_lane = 14,
+ .device_number = PCI_SLOT(WLAN_DEVFN),
+ .function_number = PCI_FUNC(WLAN_DEVFN),
+ .link_speed_capability = GEN3,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ0,
+ },
+ { /* SD */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 15,
+ .end_logical_lane = 15,
+ .device_number = PCI_SLOT(SD_DEVFN),
+ .function_number = PCI_FUNC(SD_DEVFN),
+ .link_speed_capability = GEN1,
+ .turn_off_unused_lanes = true,
+ .link_hotplug = 3,
+ .clk_req = CLK_REQ1,
+ },
+ { /* SSD */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 16,
+ .end_logical_lane = 19,
+ .device_number = PCI_SLOT(NVME_DEVFN),
+ .function_number = PCI_FUNC(NVME_DEVFN),
+ .link_speed_capability = GEN_MAX,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ3,
+ },
+};
+
+static const fsp_ddi_descriptor myst_ddi_descriptors[] = {
+ { /* DDI0 - eDP */
+ .connector_type = DDI_EDP,
+ .aux_index = DDI_AUX1,
+ .hdp_index = DDI_HDP1
+ },
+ { /* DDI1 - HDMI/DP */
+ .connector_type = DDI_HDMI,
+ .aux_index = DDI_AUX2,
+ .hdp_index = DDI_HDP2
+ },
+ { /* DDI2 - DP (type C) */
+ .connector_type = DDI_DP_W_TYPEC,
+ .aux_index = DDI_AUX3,
+ .hdp_index = DDI_HDP3,
+ },
+ { /* DDI3 - DP (type C) */
+ .connector_type = DDI_DP_W_TYPEC,
+ .aux_index = DDI_AUX4,
+ .hdp_index = DDI_HDP4,
+ },
+ { /* DDI4 - Unused */
+ .connector_type = DDI_UNUSED_TYPE,
+ .aux_index = DDI_AUX5,
+ .hdp_index = DDI_HDP5,
+ },
+};
+
void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
- /* TODO(b/276744321): Initialize DXIO and DDI descriptors */
+ *dxio_descs = myst_dxio_descriptors;
+ *dxio_num = ARRAY_SIZE(myst_dxio_descriptors);
+ *ddi_descs = myst_ddi_descriptors;
+ *ddi_num = ARRAY_SIZE(myst_ddi_descriptors);
}
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index e4a2841..ae5f341 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -73,7 +73,22 @@
.speed = I2C_SPEED_FAST,
}"
+ # general purpose PCIe clock output configuration
+ register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
+ register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD
+ register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WWAN
+ register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD
+ register "gpp_clk_config[4]" = "GPP_CLK_OFF" # SOC_FP_BOOT0 GPIO
+ register "gpp_clk_config[5]" = "GPP_CLK_OFF" # WLAN_AUX_RST_L GPIO
+ register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO
+
+ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
+
device domain 0 on
+ device ref gpp_bridge_2_1 on end # WWAN
+ device ref gpp_bridge_2_2 on end # WLAN
+ device ref gpp_bridge_2_3 on end # SD
+ device ref gpp_bridge_2_4 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
index d5c2513..6ce35bb 100644
--- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,13 @@
#define __BASEBOARD_VARIANTS_H__
#include <gpio.h>
+#include <platform_descriptors.h>
+#include <soc/pci_devs.h>
+
+#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN
+#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN
+#define SD_DEVFN PCIE_GPP_2_3_DEVFN
+#define NVME_DEVFN PCIE_GPP_2_4_DEVFN
/* This function provides base GPIO configuration table. */