haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index c99bb6f..975ad39 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -21,9 +21,9 @@
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -70,5 +70,5 @@
},
};
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 5ce0145..b4d4429 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -21,9 +21,9 @@
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -70,5 +70,5 @@
},
};
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 4218393..5496092 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
@@ -43,9 +42,9 @@
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -100,6 +99,5 @@
},
};
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index a24f5c4..2231921 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
@@ -43,9 +42,9 @@
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -73,8 +72,7 @@
.usb_xhci_on_resume = 1,
};
- variant_romstage_entry(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(&pei_data);
+ variant_romstage_entry(pei_data);
}
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 88636c4..6268417 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -2,7 +2,6 @@
#include <stdint.h>
#include <stddef.h>
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
@@ -45,9 +44,9 @@
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -112,6 +111,5 @@
},
};
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 0943f1d..050d465 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
-#include <arch/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <option.h>
@@ -43,9 +43,9 @@
}
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -92,5 +92,5 @@
},
};
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 2e3f42e..6c12266 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/intel/haswell/haswell.h>
-#include <arch/romstage.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <stdint.h>
@@ -20,9 +20,9 @@
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -68,5 +68,5 @@
},
};
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 6eb8de5..baa4f32 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,8 +189,6 @@
void intel_northbridge_haswell_finalize_smm(void);
-struct pei_data;
-void romstage_common(struct pei_data *pei_data);
void mb_late_romstage_setup(void); /* optional */
void haswell_early_initialization(void);
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 920ee0f..140ea20 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -8,6 +8,9 @@
/* Optional function to copy SPD data for on-board memory */
void copy_spd(struct pei_data *peid);
+/* Necessary function to initialize pei_data with mainboard-specific settings */
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+
void sdram_initialize(struct pei_data *pei_data);
void setup_sdram_meminfo(struct pei_data *pei_data);
int fixup_haswell_errata(void);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 46633d1..b2f8e23 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/romstage.h>
#include <console/console.h>
#include <cf9_reset.h>
#include <timestamp.h>
@@ -22,10 +23,16 @@
{
}
-void romstage_common(struct pei_data *pei_data)
+/* The romstage entry point for this platform is not mainboard-specific, hence the name */
+void mainboard_romstage_entry(void)
{
int wake_from_s3;
+ struct pei_data pei_data = {
+ };
+
+ mainboard_fill_pei_data(&pei_data);
+
enable_lapic();
wake_from_s3 = early_pch_init();
@@ -52,15 +59,15 @@
post_code(0x3a);
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
- pei_data->boot_mode = wake_from_s3 ? 2 : 0;
+ pei_data.boot_mode = wake_from_s3 ? 2 : 0;
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();
- copy_spd(pei_data);
+ copy_spd(&pei_data);
- sdram_initialize(pei_data);
+ sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
@@ -71,7 +78,7 @@
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
- save_mrc_data(pei_data);
+ save_mrc_data(&pei_data);
} else if (cbmem_initialize()) {
#if CONFIG(HAVE_ACPI_RESUME)
/* Failed S3 resume, reset to come up cleanly */
@@ -81,7 +88,7 @@
haswell_unhide_peg();
- setup_sdram_meminfo(pei_data);
+ setup_sdram_meminfo(&pei_data);
romstage_handoff_init(wake_from_s3);