commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
author Keith Hui <buurin@gmail.com> Sat Jul 22 12:49:05 2023 -0400
committer Felix Held <felix-coreboot@felixheld.de> Mon Nov 13 20:31:23 2023 +0000
tree 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73
parent 940fe080bf1ed2dac827b569c70fb0ea11496041

mb/*: Update SPD mapping for sandybridge boards

Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.

Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.

Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

src/mainboard/lenovo/x220/devicetree.cb

diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 049eea6..b6736d2 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -15,6 +15,7 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 	register "ec_present" = "1"		# I have an embedded controller
 	register "max_mem_clock_mhz" = "666"	# So DDR3 freq = 1333