| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da | [log] [tgz] |
|---|---|---|
| author | Keith Hui <buurin@gmail.com> | Sat Jul 22 12:49:05 2023 -0400 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Mon Nov 13 20:31:23 2023 +0000 |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 [diff] [blame] |
mb/*: Update SPD mapping for sandybridge boards Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb index 3e1c90ee..4e03e75 100644 --- a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
@@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH device pci 1c.6 on end # PCIe Port #7 USB 3.0