| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da | [log] [tgz] |
|---|---|---|
| author | Keith Hui <buurin@gmail.com> | Sat Jul 22 12:49:05 2023 -0400 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Mon Nov 13 20:31:23 2023 +0000 |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 [diff] [blame] |
mb/*: Update SPD mapping for sandybridge boards Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 37304f2..f4e948f 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -13,6 +13,7 @@ # 1333MHz RAM frequency register "max_mem_clock_mhz" = "666" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" register "usb_port_config" = "{ {1, 0, 0x0040},