soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index a93a38a..1fa7d2f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -120,11 +120,13 @@
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
+ register "PcieRpSlotImplemented[8]" = "1"
# Enable Optane PCIE 11 using clk 0
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "HybridStorageMode" = "0"
+ register "PcieRpSlotImplemented[10]" = "1"
# Enable SD Card PCIE 8 using clk 3
register "PcieRpEnable[7]" = "1"
@@ -138,6 +140,7 @@
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieRpSlotImplemented[6]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"