soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller
- Correctly detect device 17h as the MMC 4.5 controller
- Support detection of the "old" MMC controller at device 10h
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c7bc0b6..1ebf1e8 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -59,12 +59,13 @@
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
+ device pci 10.0 off end # MMC
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
+ device pci 17.0 on end # MMC45
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index b5c4f73..a4ec620 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -5,20 +5,20 @@
#include <soc/pm.h>
#define PCI_DEV_PIRQ_ROUTES \
- PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
- PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
- PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
- PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, DISABLE), \
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index 623b149..e8253e0 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -52,5 +52,5 @@
static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = MMC_DEVID,
+ .device = MMC45_DEVID,
};
diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h
index 0437b2c..74acb8e 100644
--- a/src/soc/intel/baytrail/include/soc/pci_devs.h
+++ b/src/soc/intel/baytrail/include/soc/pci_devs.h
@@ -13,6 +13,10 @@
#define GFX_DEV 0x2
#define GFX_FUNC 0
+/* MMC Port */
+#define MMC_DEV 0x10
+#define MMC_FUNC 0
+
/* SDIO Port */
#define SDIO_DEV 0x11
#define SDIO_FUNC 0
@@ -33,9 +37,9 @@
#define LPE_DEV 0x15
#define LPE_FUNC 0
-/* MMC Port */
-#define MMC_DEV 0x17
-#define MMC_FUNC 0
+/* MMC45 Port */
+#define MMC45_DEV 0x17
+#define MMC45_FUNC 0
/* Serial IO 1 */
#define SIO1_DEV 0x18
@@ -103,6 +107,7 @@
#define SOC_DEVID 0x0f00
#define GFX_DEVID 0x0f31
+#define MMC_DEVID 0x0f14
#define SDIO_DEVID 0x0f15
#define SD_DEVID 0x0f16
#define IDE1_DEVID 0x0f20
@@ -111,7 +116,7 @@
#define AHCI2_DEVID 0x0f23
#define XHCI_DEVID 0x0f35
#define LPE_DEVID 0x0f28
-#define MMC_DEVID 0x0f50
+#define MMC45_DEVID 0x0f50
#define SIO_DMA1_DEVID 0x0f40
#define I2C1_DEVID 0x0f41
#define I2C2_DEVID 0x0f42
diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h
index 5886fe5..dc8a7fa 100644
--- a/src/soc/intel/baytrail/include/soc/pm.h
+++ b/src/soc/intel/baytrail/include/soc/pm.h
@@ -66,9 +66,10 @@
# define HSUART1_DIS (1 << 3)
# define HSUART2_DIS (1 << 4)
# define SPI_DIS (1 << 5)
+# define MMC_DIS (1 << 8)
# define SDIO_DIS (1 << 9)
# define SD_DIS (1 << 10)
-# define MMC_DIS (1 << 11)
+# define MMC45_DIS (1 << 11)
# define HDA_DIS (1 << 12)
# define LPE_DIS (1 << 13)
# define OTG_DIS (1 << 14)
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 9a297aa..a836d41 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -204,6 +204,9 @@
uint32_t mask2 = 0;
switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(MMC_DEV, MMC_FUNC):
+ mask |= MMC_DIS;
+ break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
mask |= SDIO_DIS;
break;
@@ -221,8 +224,8 @@
case PCI_DEVFN(LPE_DEV, LPE_FUNC):
mask |= LPE_DIS;
break;
- case PCI_DEVFN(MMC_DEV, MMC_FUNC):
- mask |= MMC_DIS;
+ case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
+ mask |= MMC45_DIS;
break;
case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
mask |= SIO_DMA1_DIS;
@@ -362,13 +365,16 @@
* Work around this by hard coding the offset.
*/
switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(MMC_DEV, MMC_FUNC):
+ offset = 0x80;
+ break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(SD_DEV, SD_FUNC):
offset = 0x80;
break;
- case PCI_DEVFN(MMC_DEV, MMC_FUNC):
+ case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(LPE_DEV, LPE_FUNC):