chip soc/intel/broadwell

	# Set panel power delays
	register "gpu_panel_power_cycle_delay_ms" = "400"
	register "gpu_panel_power_up_delay_ms" = "40"
	register "gpu_panel_power_down_delay_ms" = "15"
	register "gpu_panel_power_backlight_on_delay_ms" = "7"
	register "gpu_panel_power_backlight_off_delay_ms" = "210"

	device domain 0 on
		chip soc/intel/broadwell/pch
			# DTLE DATA / EDGE values
			register "sata_port0_gen3_dtle" = "0x5"
			register "sata_port1_gen3_dtle" = "0x5"

			device pci 1f.2 on  end # SATA Controller
		end
	end
end