soc/amd/genoa: Hook up MCA code
This patch uses AMD SoC common code for MCA and adds MCA bank
information as per Genoa Processor Programming Reference (PPR)
version 0.25 (#55901) and uses AMD SoC common code.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If728d803d600f7e86507cd1b35b40022bf4d379e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76524
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 397a81f..210b3e5 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -22,6 +22,7 @@
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_LPC
+ select SOC_AMD_COMMON_BLOCK_MCAX
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 96acc43..33a4061 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -18,6 +18,7 @@
ramstage-y += domain.c
ramstage-y += root_complex.c
ramstage-y += smihandler.c
+ramstage-y += mca.c
smm-y += smihandler.c
diff --git a/src/soc/amd/genoa/cpu.c b/src/soc/amd/genoa/cpu.c
index 8a7d8e9..6a07c34 100644
--- a/src/soc/amd/genoa/cpu.c
+++ b/src/soc/amd/genoa/cpu.c
@@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h>
+#include <amdblocks/mca.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <soc/cpu.h>
static void model_19_init(struct device *dev)
{
+ check_mca();
set_cstate_io_addr();
}
diff --git a/src/soc/amd/genoa/mca.c b/src/soc/amd/genoa/mca.c
new file mode 100644
index 0000000..9a6df2b
--- /dev/null
+++ b/src/soc/amd/genoa/mca.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/mca.h>
+#include <cpu/x86/msr.h>
+#include <types.h>
+
+/* TODO: Check if non-core MCA banks are same for all cores */
+static const char *const mca_bank_name[] = {
+ [0] = "Load-store unit",
+ [1] = "Instruction fetch unit",
+ [2] = "L2 cache unit",
+ [3] = "Decode unit",
+ [4] = "",
+ [5] = "Execution unit",
+ [6] = "Floating point unit",
+ [7] = "L3 cache unit",
+ [8] = "L3 cache unit",
+ [9] = "L3 cache unit",
+ [10] = "L3 cache unit",
+ [11] = "L3 cache unit",
+ [12] = "L3 cache unit",
+ [13] = "L3 cache unit",
+ [14] = "L3 cache unit",
+ [15] = "Microprocessor5 Management Controller",
+ [16] = "Parameter Block",
+ [17] = "GMI Controller",
+ [18] = "GMI Controller",
+ [19] = "High Speed Interface Unit (GMI)",
+ [20] = "High Speed Interface Unit (GMI)",
+ [21] = "Unified Memory Controller",
+ [22] = "Unified Memory Controller",
+ [23] = "Coherent Station",
+ [24] = "Coherent Station",
+ [25] = "Northbridge IO Unit",
+ [26] = "PCIe Root Port",
+ [27] = "PCIe Root Port",
+ [28] = "Power Management, Interrupts, Etc.",
+ [29] = "SMU",
+ [30] = "XGMI Controller",
+ [31] = "High Speed Interface Unit (XGMI)",
+};
+
+bool mca_has_expected_bank_count(void)
+{
+ return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count();
+}
+
+bool mca_is_valid_bank(unsigned int bank)
+{
+ return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL);
+}
+
+const char *mca_get_bank_name(unsigned int bank)
+{
+ if (mca_is_valid_bank(bank))
+ return mca_bank_name[bank];
+ else
+ return "";
+}