nb/intel/sandybridge: Update pei_data comments
Update outdated comments.
Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 1080689..26b9dcc 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -148,7 +148,6 @@
die("SPD data not found.");
if (spd_file_len < (spd_index + 1) * 256)
die("Missing SPD data.");
- // leave onboard dimm address at f0, and copy spd data there.
return spd_data[spd_index];
}
@@ -198,7 +197,6 @@
},
};
*pei_data = pei_data_template;
- // leave onboard dimm address at f0, and copy spd data there.
memcpy(pei_data->spd_data[0], locate_spd(), 256);
}
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 0a60707..8e98bec 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -105,9 +105,10 @@
uint16_t usb_port_config[16][3];
/* See the usb3 struct above for details */
pch_usb3_controller_settings usb3;
- /* SPD data array for onboard RAM. Specify address 0xf0,
- * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
- * spd_address for a given "DIMM".
+ /* SPD data array for onboard RAM.
+ * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled"
+ * flag and the spd_addresses are used to determine which DIMMs should
+ * use the SPD from spd_data[0].
*/
uint8_t spd_data[4][256];
tx_byte_func tx_byte;