soc/amd: Use common reset code for CZN & MDN SoCs
This switches the Cezanne & Mendocino SoCs to use the common reset code.
This patch does not change any behavior on those chips.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 35c2927..e1ab7b8 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -55,6 +55,7 @@
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+ select SOC_AMD_COMMON_BLOCK_RESET
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SMM