drivers/genesyslogic/gl9763e: Fix boot on eMMC failed issue on Volteer
Booting on Kingston (EMMC64G-TA29/TX29-HP) and Hynix (H26M74002HMR) eMMC
currently fails due to R/W error. This is a workaround to finetune the
data latch timing by verdor-specific setting of GL9763E. For improving
the compatibility of GL9763E with these two eMMC.
Signed-off-by: Renius Chen <reniuschengl@gmail.com>
Change-Id: Iddb145ed6a9edb2d7a50248e64659cda78b88ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c
index 48e520b..d19cc4a 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.c
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c
@@ -12,6 +12,8 @@
static void gl9763e_init(struct device *dev)
{
+ uint32_t ver;
+
printk(BIOS_INFO, "GL9763E: init\n");
pci_dev_init(dev);
@@ -25,6 +27,12 @@
pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM);
/* Enable SSC */
pci_or_config32(dev, PLL_CTL, PLL_CTL_SSC);
+ /* Check chip version */
+ ver = pci_read_config32(dev, HW_VER_2);
+ if ((ver & HW_VER_MASK) == REVISION_03) {
+ /* Set clock source for RX path */
+ pci_update_config32(dev, SD_CLKRX_DLY, ~CLK_SRC_MASK, AFTER_OUTPUT_BUFF);
+ }
/* Set VHS to read-only */
pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R);
}
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h
index fd9c6ba..5cdaa68 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.h
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h
@@ -21,3 +21,11 @@
#define PLL_CTL_2 0x93C
#define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16)
#define MAX_SSC_30000PPM (0xF5C3 << 16)
+
+#define HW_VER_2 0x8F8
+#define HW_VER_MASK 0xFFFF
+#define REVISION_03 0x0011
+
+#define SD_CLKRX_DLY 0x934
+#define CLK_SRC_MASK (0x3 << 24)
+#define AFTER_OUTPUT_BUFF (0x0 << 24)