diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c
index ade1ef6..bd5fefb 100644
--- a/src/soc/intel/cannonlake/vr_config.c
+++ b/src/soc/intel/cannonlake/vr_config.c
@@ -178,108 +178,108 @@
  *  The above values in () are for baseline.
  */
 
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_Y) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) { /* undocumented */
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_8) { /* undocumented */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 35, 35) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
 	{ 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_8_2) {
 	{ 65, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
 	{ 65, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_4_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{125, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
 	{125, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
@@ -288,7 +288,7 @@
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{125, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
 	{125, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
@@ -297,304 +297,304 @@
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 102, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35) },
 };
 
 static const struct vr_lookup vr_config_icc[] = {
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_U),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_Y),
+	VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_2),
 };
 
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) {
+VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y) {
+VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_Y) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { /* unspecified */
+VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_4) { /* unspecified */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 0, 0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { /* unspecified */
+VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_2) { /* unspecified */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 0, 0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H_8_2) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H_4_2) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{125, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
 
 
 static const struct vr_lookup vr_config_ll[] = {
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_U),
+	VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_Y),
+	VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_2),
 };
 
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT) {
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_8_2) {
 	{ 65, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 146, 25, 25) },
 	{ 65, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 117, 25, 25) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10,  86, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_4_2) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 60, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{125, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 132, 28, 28) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 104, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 68, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 42, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 38, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 25, 28, 28) },
 };
 
 static const struct vr_lookup vr_config_tdc[] = {
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_2),
 };
 
 static uint16_t get_sku_voltagelimit(int domain)