commit 432ac615d018465e9808be4286c0caf2ca192cf1
author Arthur Heymans <arthur@aheymans.xyz> Tue Jun 13 14:17:05 2017 +0200
committer Martin Roth <martinroth@google.com> Fri Jun 16 16:03:14 2017 +0200
tree 1cfc47666bf6b0673e41a192c9101ff6f12a7130
parent 24c3fef31bf08fd8023d7ef89882b271e41cc085

soc/intel/skylake: Don't allow user to change DCACHE base and size

Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>

src/soc/intel/skylake/Kconfig

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 26f9021..fb2d94b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -127,11 +127,11 @@
 	default 36
 
 config DCACHE_RAM_BASE
-	hex "Base address of cache-as-RAM"
+	hex
 	default 0xfef00000
 
 config DCACHE_RAM_SIZE
-	hex "Length in bytes of cache-as-RAM"
+	hex
 	default 0x40000
 	help
 	  The size of the cache-as-ram region required during bootblock