libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 8d8336f..90aeeeb 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -46,6 +46,7 @@
#include <libpayload-config.h>
#include <cbgfx.h>
#include <commonlib/bsd/fmap_serialized.h>
+#include <commonlib/bsd/mem_chip_info.h>
#include <ctype.h>
#include <die.h>
#include <endian.h>
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 376f298..eba4b892 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -83,6 +83,7 @@
uintptr_t compiler;
uintptr_t linker;
uintptr_t assembler;
+ uintptr_t mem_chip_base;
uintptr_t cb_version;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 72d7664..f5695d6 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -260,6 +260,9 @@
case CBMEM_ID_TYPE_C_INFO:
info->type_c_info = cbmem_entry->address;
break;
+ case CBMEM_ID_MEM_CHIP_INFO:
+ info->mem_chip_base = cbmem_entry->address;
+ break;
default:
break;
}
diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
new file mode 100644
index 0000000..7194f70
--- /dev/null
+++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+#ifndef _COMMONLIB_BSD_MEM_CHIP_INFO_H_
+#define _COMMONLIB_BSD_MEM_CHIP_INFO_H_
+
+enum mem_chip_type {
+ MEM_CHIP_DDR3 = 0x30,
+ MEM_CHIP_LPDDR3 = 0x38,
+ MEM_CHIP_DDR4 = 0x40,
+ MEM_CHIP_LPDDR4 = 0x48,
+ MEM_CHIP_LPDDR4X = 0x49,
+};
+
+struct mem_chip_info {
+ uint8_t type; /* enum mem_chip_type */
+ uint8_t num_channels;
+ uint8_t reserved[6];
+ struct {
+ uint64_t density;
+ uint8_t io_width;
+ uint8_t manufacturer_id;
+ uint8_t revision_id[2];
+ uint8_t reserved[4];
+ uint8_t serial_id[8]; /* LPDDR5 only */
+ } channel[0];
+};
+
+#endif /* _COMMONLIB_BSD_MEM_CHIP_INFO_H_ */