memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld
index 8209433..d9c2a71 100644
--- a/src/mainboard/emulation/qemu-power9/memlayout.ld
+++ b/src/mainboard/emulation/qemu-power9/memlayout.ld
@@ -30,5 +30,5 @@
#if ENV_RAMSTAGE
STACK(0xa000000, 32K)
#endif
- RAMSTAGE(0xa008000, 1M)
+ RAMSTAGE(0xa008000, 2M)
}
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 7ec4892..b74c0bb 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -16,5 +16,5 @@
/* hole at (START + 8M + 14K, 50K) */
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
- RAMSTAGE(START + 8M + 200K, 256K)
+ RAMSTAGE(START + 8M + 200K, 2M)
}
diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld
index 41f0914..325524e 100644
--- a/src/soc/cavium/cn81xx/memlayout.ld
+++ b/src/soc/cavium/cn81xx/memlayout.ld
@@ -30,9 +30,9 @@
SRAM_END(BOOTROM_OFFSET + 0x80000)
TTB(BOOTROM_OFFSET + 0x80000, 512K)
- RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
+ RAMSTAGE(BOOTROM_OFFSET + 0x100000, 2M)
/* Stack for secondary CPUs */
- REGION(stack_sec, BOOTROM_OFFSET + 0x180000,
+ REGION(stack_sec, BOOTROM_OFFSET + 0x300000,
CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000)
/* Leave some space for the payload */
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index 8dce428..224dbda 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -42,5 +42,5 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 1M)
- RAMSTAGE(0x40200000, 256K)
+ RAMSTAGE(0x40200000, 2M)
}
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index 3908426..c5d9d08 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -44,7 +44,7 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 1M)
- RAMSTAGE(0x40200000, 256K)
+ RAMSTAGE(0x40200000, 2M)
BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
index f8bb0fa..f927b60 100644
--- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -62,7 +62,7 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
- RAMSTAGE(0x40300000, 256K)
+ RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index 8d1f2bd..ed3b71b 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -66,7 +66,7 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
- RAMSTAGE(0x40300000, 256K)
+ RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index 6c238c7..b1beef0 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -54,7 +54,7 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
- RAMSTAGE(0x40300000, 256K)
+ RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
index 322844d..06806c5 100644
--- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
@@ -65,7 +65,7 @@
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
- RAMSTAGE(0x40300000, 256K)
+ RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld
index ed386f1..6f507ae 100644
--- a/src/soc/nvidia/tegra124/memlayout.ld
+++ b/src/soc/nvidia/tegra124/memlayout.ld
@@ -29,6 +29,6 @@
DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M)
- RAMSTAGE(0x80200000, 128K)
+ RAMSTAGE(0x80200000, 2M)
DMA_COHERENT(0x90000000, 2M)
}
diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld
index 55da129..e272c7d 100644
--- a/src/soc/nvidia/tegra210/memlayout.ld
+++ b/src/soc/nvidia/tegra210/memlayout.ld
@@ -32,6 +32,6 @@
DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M)
- RAMSTAGE(0x80200000, 256K)
+ RAMSTAGE(0x80200000, 2M)
TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
}
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld
index e630e74..4b56060 100644
--- a/src/soc/qualcomm/ipq40xx/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/memlayout.ld
@@ -44,6 +44,6 @@
DRAM_START(0x80000000)
SYMBOL(memlayout_cbmem_top, 0x87280000)
POSTRAM_CBFS_CACHE(0x87280000, 512K)
- RAMSTAGE(0x87300000, 512K)
- DMA_COHERENT(0x87400000, 2M)
+ RAMSTAGE(0x87300000, 2M)
+ DMA_COHERENT(0x87500000, 2M)
}
diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld
index 793e74e..43a51da 100644
--- a/src/soc/qualcomm/ipq806x/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/memlayout.ld
@@ -32,7 +32,7 @@
SRAM_END(0x2A060000)
DRAM_START(0x40000000)
- RAMSTAGE(0x40640000, 128K)
+ RAMSTAGE(0x40640000, 2M)
SYMBOL(memlayout_cbmem_top, 0x59F80000)
POSTRAM_CBFS_CACHE(0x59F80000, 384K)
DMA_COHERENT(0x5A000000, 2M)
diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld
index 348fb43..d883e24 100644
--- a/src/soc/qualcomm/qcs405/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/memlayout.ld
@@ -35,5 +35,5 @@
/* DDR Carveout for BL31 usage */
REGION(dram_reserved, 0x85000000, 0x5100000, 4096)
POSTRAM_CBFS_CACHE(0x9F800000, 384K)
- RAMSTAGE(0x9F860000, 128K)
+ RAMSTAGE(0x9F860000, 2M)
}
diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld
index 5e35a06..ea69a42 100644
--- a/src/soc/rockchip/rk3288/memlayout.ld
+++ b/src/soc/rockchip/rk3288/memlayout.ld
@@ -10,7 +10,7 @@
SECTIONS
{
DRAM_START(0x00000000)
- RAMSTAGE(0x00200000, 128K)
+ RAMSTAGE(0x00200000, 2M)
POSTRAM_CBFS_CACHE(0x01000000, 1M)
DMA_COHERENT(0x10000000, 2M)
FRAMEBUFFER(0x10800000, 8M)
diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld
index 142a892..c424692 100644
--- a/src/soc/samsung/exynos5250/memlayout.ld
+++ b/src/soc/samsung/exynos5250/memlayout.ld
@@ -27,7 +27,7 @@
SRAM_END(0x2078000)
DRAM_START(0x40000000)
- RAMSTAGE(0x40000000, 128K)
+ RAMSTAGE(0x40000000, 2M)
POSTRAM_CBFS_CACHE(0x41000000, 8M)
DMA_COHERENT(0x77300000, 1M)
}
diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld
index 7c89413..240cdcd 100644
--- a/src/soc/samsung/exynos5420/memlayout.ld
+++ b/src/soc/samsung/exynos5420/memlayout.ld
@@ -28,7 +28,7 @@
SRAM_END(0x2074000)
DRAM_START(0x20000000)
- RAMSTAGE(0x20000000, 128K)
+ RAMSTAGE(0x20000000, 2M)
POSTRAM_CBFS_CACHE(0x21000000, 8M)
DMA_COHERENT(0x77300000, 1M)
}
diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld
index 73faa4b..8fc875d 100644
--- a/src/soc/sifive/fu540/memlayout.ld
+++ b/src/soc/sifive/fu540/memlayout.ld
@@ -22,7 +22,7 @@
DRAM_START(FU540_DRAM)
REGION(opensbi, FU540_DRAM, 128K, 4K)
- RAMSTAGE(FU540_DRAM + 128K, 256K)
- MEM_STACK(FU540_DRAM + 448K, 20K)
- POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K)
+ RAMSTAGE(FU540_DRAM + 128K, 2M)
+ MEM_STACK(FU540_DRAM + 128K + 2M, 20K)
+ POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M)
}