stage_cache: use cbmem init hooks
Instead of having the chipset code make the approrpiate
calls at the appropriate places use the cbmem init hooks
to take the appropriate action. That way no chipset code
needs to be changed in order to support the external
stage cache.
Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10481
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0f0890a..6adb8be 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -35,7 +35,6 @@
#include <cbfs.h>
#include <romstage_handoff.h>
#include <reset.h>
-#include <stage_cache.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include <ec/google/chromeec/ec.h>
@@ -256,17 +255,13 @@
if (!wake_from_s3) {
cbmem_initialize_empty();
- stage_cache_create_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
- #if CONFIG_HAVE_ACPI_RESUME
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
- #endif
- }
+ } else if (cbmem_initialize()) {
+ #if CONFIG_HAVE_ACPI_RESUME
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
+ #endif
}
handoff = romstage_handoff_find_or_add();
diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h
index bde5330..5a4c16a 100644
--- a/src/include/stage_cache.h
+++ b/src/include/stage_cache.h
@@ -29,10 +29,6 @@
STAGE_REFCODE,
};
-/* Create an empty stage cache. */
-void stage_cache_create_empty(void);
-/* Recover existing stage cache. */
-void stage_cache_recover(void);
/* Cache the loaded stage provided according to the parameters. */
void stage_cache_add(int stage_id, struct prog *stage);
/* Load the cached stage at given location returning the stage entry point. */
diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c
index b9ee14e..4a11443 100644
--- a/src/lib/cbmem_stage_cache.c
+++ b/src/lib/cbmem_stage_cache.c
@@ -22,11 +22,6 @@
#include <stage_cache.h>
#include <string.h>
-
-/* Provide empty implementations by default. */
-void __attribute__((weak)) stage_cache_create_empty(void) {}
-void __attribute__((weak)) stage_cache_recover(void) {}
-
/* Stage cache uses cbmem. */
void stage_cache_add(int stage_id, struct prog *stage)
{
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
index 379b9fc..4e588f1 100644
--- a/src/lib/ext_stage_cache.c
+++ b/src/lib/ext_stage_cache.c
@@ -33,7 +33,7 @@
return car_get_var_ptr(&imd_stage_cache);
}
-void stage_cache_create_empty(void)
+static void stage_cache_create_empty(void)
{
struct imd *imd;
void *base;
@@ -49,7 +49,7 @@
printk(BIOS_DEBUG, "Could not limit stage cache size.\n");
}
-void stage_cache_recover(void)
+static void stage_cache_recover(void)
{
struct imd *imd;
void *base;
@@ -120,10 +120,13 @@
prog_set_entry(stage, (void *)(uintptr_t)meta->entry_addr, NULL);
}
-#if ENV_RAMSTAGE
-static void recover_sc(void *unused)
+static void stage_cache_setup(int is_recovery)
{
- stage_cache_recover();
+ if (is_recovery)
+ stage_cache_recover();
+ else
+ stage_cache_create_empty();
}
-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, recover_sc, NULL);
-#endif
+
+ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
+RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 191821a..d4f1711 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -25,7 +25,6 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <halt.h>
-#include <stage_cache.h>
#include <soc/gpio.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
@@ -169,16 +168,12 @@
if (prev_sleep_state != 3) {
cbmem_initialize_empty();
- stage_cache_create_empty();
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
- #if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
- #endif
- }
+ } else if (cbmem_initialize()) {
+ #if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
+ #endif
}
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
diff --git a/src/soc/intel/braswell/romstage/raminit.c b/src/soc/intel/braswell/romstage/raminit.c
index 191821a..d4f1711 100644
--- a/src/soc/intel/braswell/romstage/raminit.c
+++ b/src/soc/intel/braswell/romstage/raminit.c
@@ -25,7 +25,6 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <halt.h>
-#include <stage_cache.h>
#include <soc/gpio.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
@@ -169,16 +168,12 @@
if (prev_sleep_state != 3) {
cbmem_initialize_empty();
- stage_cache_create_empty();
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
- #if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
- #endif
- }
+ } else if (cbmem_initialize()) {
+ #if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
+ #endif
}
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index edc8790..82c88cb 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -29,7 +29,6 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#endif
-#include <stage_cache.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
@@ -111,16 +110,12 @@
if (pei_data->boot_mode != SLEEP_STATE_S3) {
cbmem_initialize_empty();
- stage_cache_create_empty();
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
+ } else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
#endif
- }
}
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,