diff --git a/Documentation/index.md b/Documentation/index.md
index afe892d..4ec4550 100644
--- a/Documentation/index.md
+++ b/Documentation/index.md
@@ -18,3 +18,4 @@
 * [System on Chip-specific documentation](soc/index.md)
 * [Mainboard-specific documentation](mainboard/index.md)
 * [SuperIO-specific documentation](superio/index.md)
+* [Release notes for past releases](releases/index.md)
diff --git a/Documentation/releases/coreboot-4.1-relnotes.md b/Documentation/releases/coreboot-4.1-relnotes.md
new file mode 100644
index 0000000..4bc7a39
--- /dev/null
+++ b/Documentation/releases/coreboot-4.1-relnotes.md
@@ -0,0 +1,58 @@
+Announcing coreboot 4.1
+=======================
+
+Dear coreboot community,
+
+It has been more than 5 years since we have "released" coreboot 4.0.
+That last release marked some very important milestones that we
+originally prototyped in the abandoned LinuxBIOS v3 efforts, like the
+coreboot filesystem (CBFS), Kconfig support, and (strictly) separate
+device trees, build logic and configuration.
+
+Since then there have been as many significant original developments,
+such as support for many new architectures (ARM, ARM64, MIPS, RISC-V),
+and related architectural changes like access to non-memory mapped SPI
+flash, or better insight about the internals of coreboot at runtime
+through the cbmem console, timestamp collection, or code coverage
+support.
+
+It became clear that a new release is overdue. With our new release
+process only slowly getting in shape, I decided to take a random commit
+and call it 4.1.
+
+The release itself happens at an arbitrary point in time, but will serve
+as a starting point for other activities that require some kind of
+starting point to build on, described below.
+
+Future releases will happen more frequently, and with more guarantees
+about the state of the release, like having a cool down phase where
+boards can be tested and so on. I plan to create a release every three
+months, so the changes between any two release don't become too
+overwhelming.
+
+With the release of coreboot 4.1, you get an announcement (this email),
+a git tag (4.1), and tar archives at http://www.coreboot.org/releases/,
+for the coreboot sources and the redistributable blobs.
+
+Starting with coreboot 4.1, we will maintain a high level changelog and
+'flag days' document. The latter will provide a concise list of changes
+which went into coreboot that require chipset or mainboard code to
+change to keep it working with the latest upstream coreboot.
+
+For the time being, I will run these efforts, but I'll happily share
+documentation duties with somebody else. It is a great opportunity to
+keep track of things, learn about the project and its design and various
+internals, while contributing to the project without the need to code.
+
+Please contact me (for example by email or on IRC) if you're interested,
+and we'll work out how to collaborate on this.
+
+The process should enable users of coreboot to follow releases if they
+want a more static base to build on, while making it easier to follow
+along with new developments by providing upgrade documentation.
+
+Since moving away from a rolling (non-)release model is new for
+coreboot, things may still be a bit rough around the edges, but I'll
+provide support for any issues that arise from the release process.
+
+Patrick
diff --git a/Documentation/releases/coreboot-4.2-relnotes.md b/Documentation/releases/coreboot-4.2-relnotes.md
new file mode 100644
index 0000000..4d6c670
--- /dev/null
+++ b/Documentation/releases/coreboot-4.2-relnotes.md
@@ -0,0 +1,182 @@
+Announcing coreboot 4.2
+=======================
+
+Halloween 2015 release - just as scary as that sounds
+
+Dear coreboot community,
+today marks the release of coreboot 4.2, the second release on our time
+based release schedule. Since 4.1 there were 936 commits by 90 authors,
+increasing the code base by approximately 17000 lines of code. We saw 35
+new contributors - welcome to coreboot! More than 34 developers were
+active as reviewers in that period. Thanks go to all contributors who
+helped shape this release.
+
+As with 4.1, the release tarballs are available at
+http://www.coreboot.org/releases/. There's also a 4.2 tag and branch in
+the git repository.
+
+This marks the first release that features a changelog comparing it to
+the previous release. There was some limited testing to make sure that
+the code is usable, and it boots on some devices. A structured test plan
+will only become part of the release procedure of future versions. I'm
+grateful to Martin for assembling this release's changelog.
+
+This is also the first release that will be followed by the removal of
+old, unused code. There will be a policy on how to announce deprecation
+and removal of mainboard and chipset code for future releases.
+
+Regards,
+Patrick
+
+Log of commit d5e6618a4f076610e683b174c4dd5108d960c785 to
+commit 439a527014fa0cb3e4ef60ba59e5c57c737b4444
+
+Changes between 4.1 and 4.2
+---------------------------
+
+### Build system:
+* Store a minimized coreboot config file in cbfs instead of the full
+  config
+* Store the payload config and revision in CBFS when that info is
+  available
+* Add -compression option for cbfs-files-y. Valid entries are now -file,
+  -type, -align, and -compression
+* Change Microcode inclusion method from building .h files to pre-built
+  binaries
+* Update Builder tests for each commit to test utilities and run lint
+  tools
+* Many other small makefile and build changes and fixes
+* Remove expert mode as a Kconfig option
+
+### Utilities:
+* Many fixes and updates to many utilities (158 total commits)
+* ifdtool: Update for skylake, handle region masks correctly
+* crossgcc: Update to gcc 5.2.0
+* kconfig: Add strict mode to fail on kconfig errors and warnings
+* vgabios: Significant fixes to remove issues in linking into coreboot
+  code
+* Add script to parse MAINTAINERS file
+* Add Kconfig lint tool
+* Create a common library to share coreboot routines with utilities
+
+#### Significant changes and cleanup to cbfstool (81 commits)
+* Update cbfstool to change the internal location of FSP binaries when
+  adding them
+* Decompress stage files on extraction and turn them into ELF binaries
+* Header sizes are now variable, containing extended attributes
+* Add compression tags to all cbfs headers so all cbfs files can be
+  compressed
+* Add and align CBFS components in one pass instead of two
+* Add XIP support for X86 to relocate the romstage when it'™s added
+* Removed locate command as it'™s no longer needed
+* Add bootblock and cbfs_header file types so the master header knows
+  about them
+* Prefer FMAP data to CBFS master header if FMAP data exists
+* Add hashes to cbfs file metadata for verification of images
+
+### Payloads:
+* SeaBIOS: update stable release from 1.7.5 to 1.8.2
+* Libpayload had some significant changes (61 commits). Major changes:
+* Add support for fmap tables
+* Add support for SuperSpeed (3.0) USB hubs
+* Updates and bugfixes for DesignWare OTG controller (DWC2)
+* Add video_printf to print text with specified foreground & background
+  colors
+* Updates to match changes to cbfs/cbfstool
+* Add cbgfx, a library to show graphics and text on a display
+* Read cbfs offset and size from sysinfo when available
+
+### Vendorcode:
+* fsp_baytrail: Support Baytrail FSP Gold 4 release
+* AMD binary PI: add support for fan control
+* Work to get AMD AGESA to compile correctly as 64-bit code
+* Add standalone (XIP) verstage support for x86 to verify romstage
+
+### Mainboards:
+* New Mainboards:
+* apple/macbookair4_2 * Sandy/Ivy Bridge with Panther / Cougar point
+chipset
+* asus/kgpe-d16 - AMD Family 10, SB700/SR5650 platform
+* emulation/spike-riscv - RISCV virtualized platform
+* google/chell - Intel Skylake chrome platform
+* google/cyan - Intel Braswell chrome platform
+* google/glados - Intel Skylake chrome platform
+* google/lars - Intel Skylake chrome platform
+* intel/kunimitsu - Intel Skylake chrome platform
+* intel/sklrvp - Intel Skylake reference platform
+* intel/strago - Intel Braswell chrome platform
+* Cleanups of many mainboards - several patches each for:
+* amd/bettong
+* getac/p470
+* google/auron, google/smaug and google/veyron_rialto
+* pcengines/apu1
+* siemens/mc_tcu3
+* Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark &
+  speedy) mainboards into the single google/veyron mainboard directory
+
+### Console:
+* Add EM100 ˜hyper term" spi console support in ramstage & smm
+* Add console support for verstage
+
+### ARM:
+* armv7: use asm coded memory operations for 32/16 bit read/write
+* Many cleanups to the nvidia tegra chips (40 patches)
+
+### RISC-V:
+* Add trap handling
+* Add virtual Memory setup
+
+### X86:
+* Remove and re-add Rangeley and Ivy Bridge / panther point FSP
+  platforms
+* Update microcode update parser to use stock AMD microcode blobs from
+  CBFS
+* ACPI: Align FACS to 64 byte boundary. Fixes FWTS error
+* AMD/SB700: Init devices in early boot, restore power state after power
+  failure. Add IDE/SATA asl code
+* Add initial support for AMD Socket G34 processors
+* Add tick frequency to timestamp table to calculate boot times more
+  accurately
+* Unify X86 romstage / ramstage linking to match other platforms
+* Start preparing X86 bootblock for non-memory-mapped BIOS media
+* cpu/amd/car: Add Suspend to RAM (S3) support
+* Native VGA init fixes on several platforms
+* Significant updates to FSP 1.1 code for cleanup and cbfstool changes
+* SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to
+  prevent the memory sinkhole smm hack
+
+### Drivers:
+* Add native text mode support for the Aspeed AST2050
+* w83795: Add support for for fan control and voltage monitoring
+* Intel GMA ACPI consolidation and improvements
+* Set up the 8254 timer before running option ROMs
+* Resource allocator: Page align memory mapped PCI resources
+
+### Lib:
+* Derive fmap name from offset/size
+* Several edid fixes
+* Updates to cbfs matching changes in cbfstool
+
+Submodules:
+----------
+### 3rdparty/blobs:
+Total commits: 16
+Log of commit 61d663e3 to commit aab093f0
+* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)
+* AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)
+* Update microcode to binary blobs. Remove old .h microcode files
+
+### 3rdparty/arm-trusted-firmware:
+* No Changes
+
+### 3rdparty/vboot:
+Total commits: 41
+Log of commit fbf631c8 to commit d6723ed1
+* Update the code to determine the write protect line gpio value
+* Several updates to futility and image_signing scripts
+* Update crossystem to accommodate Android mosys location
+* Support reboot requested by secdata
+* Add NV flag to default boot legacy OS
+
+### util/nvidia/cbootimage:
+* No Changes
diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md
new file mode 100644
index 0000000..2a5591c
--- /dev/null
+++ b/Documentation/releases/coreboot-4.3-relnotes.md
@@ -0,0 +1,183 @@
+Announcing coreboot 4.3
+=======================
+
+The "Oh, has FOSDEM started?" release
+
+Dear coreboot community,
+
+today marks the release of coreboot 4.3, the third release on our time
+based release schedule. Since the last release, 1030 commits by 114
+authors added a net total of 17500 lines to the source code. Thank you
+to all who contributed!
+
+The release tarballs are available at http://www.coreboot.org/releases/.
+There's also a 4.3 tag and branch in the git repository.
+
+Besides the usual addition of new mainboards (14) and chipsets
+(various), a big theme of the development since 4.2 was cleaning up the
+code: 20 mainboards were removed that aren't on the market for years
+(and even hard to get on Ebay). For several parts of the tree, we
+established tighter controls, making errors out of what were warnings
+(and cleaning up the code to match) and provided better tests for
+various aspects of the tree, and in general tried to establish a more
+consistent structure across the code base.
+
+Besides that, we had various improvements across the tree, each
+important when using the hardware, but to numerous for individual shout
+outs. Martin compiled a list that's best posted verbatim. Thanks Martin!
+
+Log of commit 529fd81f640fa514ea4c443dd561086e7c582a64 to commit
+1bf5e6409678d04fd15f9625460078853118521c for a total of 1030 commits:
+
+Mainboards
+----------
+
+### Added 14 mainboards
+
+* asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804
+  southbridge
+* esd/atom15: Bay Trail SOC mainboard using Intel's FSP
+* gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB
+* google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)
+* google/oak: Mediatek MT8173 SoC chromebook
+* google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)
+* google/veyron_emile: Rockchip RK3288 SoC board
+* intel/d510mo: Native init Intel Pineview with Intel I82801GX
+  southbridge
+* intel/littleplains: Intel Atom c2000 (Rangeley) SoC board
+* intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel's FSP
+* lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
+* lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
+* purism/librem13: Intel Broadwell Laptop using Intel MRC
+* sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB
+
+### Removed 20 mainboards
+
+* arima/hdama
+* digitallogic/adl855pc
+* ibm/e325, e326
+* intel/sklrvp
+* iwill/dk8s2, dk8x
+* newisys/khepri
+* tyan/s2735, s2850, s2875, s2880, s2881 & s2882
+* tyan/s2885, s2891, s2892, s2895, s4880 & s4882
+
+### Improvements to mainboards
+
+* amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS
+* asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART
+* intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes
+* ACPI fixes across various platforms
+* Many individual fixes to other mainboards
+
+### Continued updates for the Intel Skylake platform
+
+* google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT
+  support
+* intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support
+
+Build system
+------------
+* Update build to use FMAP based firmware layout with multiple cbfs
+  sections
+* Enable Kconfig strict mode - Kconfig warnings are no longer allowed.
+* Enable ACPI warnings are errors in IASL - warnings are no longer
+  allowed.
+* Tighten checking on toolchains and give feedback to users if there are
+  issues
+* Updates to get the ADA compiler to work correctly for coreboot
+* Various improvements to Makefiles and build scripts
+* Cleanup of CBFS file handling
+
+Utilities
+---------
+* cleanups and improvements to many of the utilities
+* cbfstool: Many fixes and extensions to integrate with FMAP
+* Add amdfwtool to combine AMD firmware blobs instead of using shell
+  scripts.
+* Toolchain updates: new versions of GMP & MPFR. Add ADA.
+* Updates for building on NetBSD & OS X
+
+Payloads
+--------
+* SeaBIOS: Update stable release to 1.9.0
+* coreinfo: fix date, hide cursor, use crosscompiler to build
+* libpayload: updates for cbfs, XHCI and DesignWare HCD controllers
+
+ARM
+---
+* Added 1 soc: mediatek/mt8173
+* Various fixes for ARM64 platforms
+
+X86
+---
+* Added 2 northbridges: intel/pineview & x4x
+* Removed 1 northbridge: intel/i440lx
+* Added 1 southbridge: intel/fsp_i89xx
+* Removed 2 southbridge(s): intel/esb6300 & i82801cx
+* Rename amd/model_10xxx to family_10h-family_15h.
+* ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET
+  entries
+* Work in many areas fixing issues compiling in 64-bit
+* Numerous other fixes across the tree
+
+Areas with significant work on updates and fixes
+------------------------------------------------
+* cpu/amd/model_fxx
+* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode
+* nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other
+  changes
+* nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other
+  changes
+* nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup
+* soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes
+* soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.
+* soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support
+* sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes
+
+MIPS
+----
+* Imgtec Pistachio: Memory, PLL & I2C fixes, add reset
+
+SuperIO
+-------
+* Expand functionality for ite/it8718f & nuvoton/nct5572d superio
+  devices
+
+### Added 3 SIOs
+
+* intel/i8900
+* winbond/w83667hg-a & wpcd376i
+
+### Removed 6 SIOs
+
+* fintek/f71889
+* ite/it8661f
+* nsc/pc8374 & pc97307
+* nuvoton/nct6776
+* smsc/fdc37m60x
+
+Lib
+---
+* Several updates for reading EDID tables
+
+MISC
+----
+* Commonlib: continued updates for cbfs changes
+* Work on getting license headers on all coreboot files
+* Drop the third paragraph of GPL copyright header across all of
+  coreboot
+
+Submodules
+----------
+* 3rdparty/blobs: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)
+
+coreboot statistics
+-------------------
+Total commits: 1030
+Total authors: 114
+New authors: 46
+Total Reviewers: 41
+Total lines added: 88255
+Total lines removed: -70735
+Total delta: 17520
diff --git a/Documentation/releases/coreboot-4.4-relnotes.md b/Documentation/releases/coreboot-4.4-relnotes.md
new file mode 100644
index 0000000..8b67f5f
--- /dev/null
+++ b/Documentation/releases/coreboot-4.4-relnotes.md
@@ -0,0 +1,110 @@
+Announcing coreboot 4.4
+=======================
+
+We are happy to announce the release of coreboot 4.4.  This is our
+fourth quarterly release.  Since the last release, we've had 850 commits
+by 90 authors adding 59000 lines to the codebase.
+
+The release tarballs are available at https://www.coreboot.org/releases/
+There is a 4.4 tag and branch in the git repository.
+
+Log of commit 3141eac900 to commit 588ccaa9a7
+
+Major areas that received significant changes in for this release:
+* Build system (30 commits) - Add postcar stage, 'timeless' builds,
+  extend site-local, test toolchain by version string, update
+  dependencies, catch ACPI errors, add additional macros.
+* Toolchain updates (40+ patches) - Update IASL to v20160318 , LLVM to
+  v3.7.1, add GNU make, add nds32le GCC compiler
+* Lint tools (30 patches) - Update existing lint utilities, add lint
+  tests for executable bit, make sure site-local isn't committed, add
+  test to break all lint tests.
+* Payloads (60 commits) - Fixes for libpayload, coreinfo and nvramcui,
+  add new payloads, see below.
+* Maintainers file - (8 patches) - continue adding maintainers for
+  various areas.
+* Documentation for adding Intel FSP-based platforms (20 commits)
+
+Mainboards
+----------
+### Added 9 mainboards
+* asus/kcma-d8
+* emulation/qemu-power8
+* google/auron_paine
+* google/gru
+* intel/amenia
+* intel/apollolake_rvp
+* intel/camelbackmountain_fsp
+* intel/galileo
+* lenovo/t420
+
+### Existing boards with significant updates
+* asus/kgpe-d16
+* google/oak
+* google/chell
+* intel/kunimitsu
+
+Changes in chips
+----------------
+### Added 1 new architecture
+* power8
+
+### Added 1 processor
+* qemu-power8
+
+### Added 5 socs
+* intel/apollolake
+* intel/fsp_broadwell_de
+* intel/quark
+* marvell/armada38x
+* rockchip/rk3399
+
+### Existing chip areas with many changes
+* cpuamd/mct_ddr3
+* drivers/intel/fsp2_0
+* northbridge/intel/sandybridge/raminit
+* soc/intel/apollolake
+* soc/intel/fsp_baytrail
+* soc/intel/skylake
+* soc/mediatek/mt8173
+
+### Added 1 new vendorcode directory
+* siemens
+
+Submodules
+----------
+### Added 1 submodule
+* chromeec
+
+### Updated 3 submodules
+* 3rdparty/arm-trusted-firmware (329 commits)
+* 3rdparty/vboot (28 commits)
+* util/nvidia/cbootimage (13 commits)
+
+Other
+-----
+### Added 4 payloads
+* depthcharge: For ChromeOS verified boot
+* iPXE: For network booting
+* Memtest86+: Updated with fixes for correctly testing coreboot with
+  payloads
+* U-Boot (Experimental): Alternate payload for booting an OS
+
+### Added 6 utilities
+* archive - Concatenates files into a single blob with an indexed header
+* chromeos - Download and extract blobs from a ChromeOS image
+* futility - vboot Firmware utility
+* intelmetool - Shows information about the Intel ME on a platform.
+* marvell/doimage_mv - No usage notes
+* post - Simple utility to test post cards
+
+coreboot statistics
+-------------------
+* Total Commits:          850
+* Total authors:           90
+* New authors:             28
+* Total Reviewers:         40
+* Total Submitters:        17
+* Total lines added:    74054
+* Total lines removed: -15056
+* Total difference:     58998
diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md
new file mode 100644
index 0000000..31eac0a
--- /dev/null
+++ b/Documentation/releases/coreboot-4.5-relnotes.md
@@ -0,0 +1,214 @@
+Announcing coreboot 4.5
+=======================
+
+We are happy to announce the release of coreboot 4.5
+
+The 4.5 release covers commit 80a3df260767 to commit 0bc12abc2b26.
+
+This release is the first since the project switched from doing
+quarterly releases to doing biannual releases.  The next release will be
+in April of 2017.
+
+Since the last release in April, the coreboot project has had 1889
+commits by 119 authors.
+
+The release tarballs and gpg signatures are available in the usual place
+at https://www.coreboot.org/downloads
+
+There is a 4.5 tag in the git repository, and a branch will be created
+as needed.
+
+
+Areas with significant updates
+------------------------------
+
+### Toolchain (29 commits)
+* Updated mpfr version from 3.1.3 to 3.1.4
+* Updated gcc version from 5.2.0 to 5.3.0
+* Updated binutils version from 2.25 to 2.26.1 & Fix aarch64 build
+  problem
+* Updated gdb version from 7.9.1 to 7.11
+* Updated iasl version from 20160318 to 20160831
+* Updated python version from 3.4.3 to 3.5.1
+* Updated expat version from 2.1.0 to 2.1.1
+* Updated llvm / clang version from 3.7.1 to 3.8.0
+* Updated make version from 4.1 to 4.2.1
+
+### Build system (32 commits)
+* Updates for cbfstool / fmap changes
+* Order per-region files to optimize placement success
+* Add support for the ADA language and toolchain.
+
+### Utilities (103 commits)
+* Lint - Update checkpatch.pl, add tools  to find non-ascii &
+  unprintable chars and to verify a single newline at the end of files
+* cbfstool - Update for Linux payloads, Honor FSP modules addresses, fix
+  elf parsing
+* Sconfig - Add 10 bit addressing mode for i2c devices, add generic
+  device type, support strings, pass in devicetree filename
+* General code cleanup (197 commits)
+* Cleaning up code formatting and whitespace
+* Fix spelling & capitalization
+* Removing commented out code
+* Transition away from device_t
+
+### TPM (55 commits)
+* Add support for Trusted Platform Module 2.0
+* SPI & refactored I2C TPM driver
+
+### Drivers (54 commits)
+* Add ACPI support in several drivers
+* coreboot_tables -  Extend serial port description
+* Elog - refactor, add debug info
+* I2C - add generic driver,
+* SPI - Add new chip support, major refactoring, don't assume SPI flash
+  boot device
+
+### Lib (33 commits)
+* Add real-time-clock functions
+* Add RW boot device construct
+* reg_script updates: add to bootblock, add xor support, add display
+  support
+* Timestamp fixes & updates
+
+### Vendorcode
+* AMD (14 commits) - Cleanup, add libagesa.a builds, remove unused code.
+* Google (22 commits) - VBoot2 updates and cleanup
+* Intel (86 commits) - Add Intel FSP 2.0, update Broadwell DE support
+
+### Payloads (37 commits)
+* Subpayload support got extend and is enabled by default.
+* nvramcui: refactor, update build
+* SeaBIOS: Update stable version to 1.9.3, add bootorder file
+* iPXE: Update stable version to the last commit of July 2016
+* Fix broken linux boot sequence
+
+Mainboard changes
+-----------------
+
+### Added 13 mainboards, plus a few mainboard variants not included here
+* ADI RCC-DFF networking board (adi/rcc-dff) - intel/rangeley SoC
+* AMD Evaluation Board DB-FT3B-LC (amd/db-ft3b-lc) - amd/00730F01
+  (Family 16h  Models 30h-3Fh (Mullins)) CPU
+* AMD f2950 / TONK 1201/2 Board (amd/f2950) - amd/geode_lx CPU
+* Apple iMAC 5.2 (apple/imac52) - intel/i945 CPU
+* Unibap Development Kit ODE E21XX - amd/00730F01 (Family 16h Models
+  30h-3Fh (Mullins)) CPU
+* elmex/pcm205400 - amd/Family_14 CPU
+* elmex/pcm205401 - amd/Family_14 CPU
+* Lenovo N21 chromebook (google/enguarde) - intel/baytrail SoC
+* google/gale - Qualcomm IPQ40XX SoC
+* AOpen Chromebox (google/ninja) - intel/baytrail SoC
+* google/reef - intel/apollolake SoC
+* Acer Chromebox CXI2 (google/rikku) - intel/Broadwell SoC
+* google/rotor - marvell/MVMAP2315 SoC
+
+### Removed 5 mainboards:
+These were all development boards not available to the public.
+* google/bolt - intel/haswell - removed in commit 139314b
+* google/rush - nvidia/tegra132 - removed in commit e67cd9e
+* google/rush_ryu - nvidia/tegra132 - removed in commit 0c63415
+* google/slippy - intel/haswell - removed in commit bc24b85
+* intel/amenia - intel/apollolake - removed in commit c2586db
+
+### Existing boards with significant updates
+* asus/kgpe-d16 - amd/socket_G34 - Add TPM support, enable secondary
+  serial port
+* emulation/spike-riscv: RISC-V -clean up, use generic bootblock, look
+  for  CBFS in RAM, reimplement SBI
+* google/gru - rockchip/RK3399 SoC (76 commits) - Board bringup
+* google/oak - mediatek/mt8173 SoC- Add Elm variant, update memory,
+  configure display, initialize touchscreen gpio
+* intel/galilleo- intel/quark SoC (14 commits) - Board bringup, add
+  galileo gen1 support, switch to FSP2.0
+* intel/minnowmax - intel/fsp_baytrail SoC - Enable all PCIe ports,
+  Program GPIO for power LED
+* lenovo/x60 - intel/socket_mPGA478 - init GPIOs before dock check, add
+  hda verb table
+* siemens/mc_bdx1 - intel/fsp_broadwell_de SoC - Add external RTC, Set
+  up MAC addresses, Update IRQs
+* siemens/mc_tcu3 - intel/fsp_baytrail SoC - cleanup & LCD panel updates
+
+Changes in chips
+----------------
+### Moved 3 northbridge/southbridge pairs to soc:
+* dmp/vortex86ex
+* intel/sch
+* rdc/r8610
+
+### Added 2 socs:
+* marvell/mvmap2315 (12 commits)
+* qualcomm/ipq40xx (22 commits)
+
+### Removed 1 soc:
+* nvidia/tegra132 - removed in commit 9ba0699
+
+### Added 2 sios:
+* nuvoton/nct6776
+* nuvoton/nct6791d
+
+### ARM (34 commits)
+* Add armv7-r configuration
+
+#### rockchip/rk3399 (73 commits)
+* Bringup, memory updates
+
+### RISC-V (40 commits)
+* Improve and refactor trap handling
+
+### X86 (225 commits)
+
+### ACPI (40 commits)
+* Add support for writing various entries and descriptor
+  types, Add common definitions, Use 'GOOG' id for coreboot table
+* amd/mct_ddr3 northbridge: Support non-ECC DIMMs, Update SMBIOS,
+  various fixes
+* arch/x86: many postcar stage updates, add common ACPI definitions,
+  Support "weak" BIST and timestamp save routines
+* intel/apollolake SoC (211 commits) - Chip bringup, Update bootblock
+* intel/common: ACPI updates, Add smihandler, LPSS I2C driver, and  IGD
+  OpRegion support
+* intel/fsp_broadwell_de: IRQ fixes, SPI message fixes, Add DMAR table
+  to ACPI
+* intel/gm45 northbridge: Fix text mode init, enable vesa framebuffer,
+  use VGA if connected
+* intel/i945 northbridge: add native VGA init, Update divisor
+  calculations
+* intel/quark SoC (62 commits) - Chip bringup, add Fsp2.0 support,
+  updates for serial console
+* intel/skylake CPU (61 commits) - Finished Skylake bringup, start
+  updating for Kabylake FSP
+* intel/x4x northbridge (13 commits) - Memory & Graphics updates
+
+Submodules
+----------
+Updated 4 submodules
+* 3rdparty/blobs (6 commits)
+* 3rdparty/arm-trusted-firmware (425 commits)
+* 3rdparty/vboot (61 commits)
+* 3rdparty/chromeec/ (676 commits)
+
+Tested boards
+-------------
+The following boards were tested for this release:
+* asrock/e350m1                 4.4-1890
+* asus/kfsn4-dre                4.4-1698 / 4.5-17
+* asus/kgpe-d16                 4.4-1802 / 4.5-17
+* emulation/qemu-q35            4.4-1698 / 4.5-8
+* gigabyte/ga-b75m-d3v          4.4-1757
+* google/peppy                  4.4-1882
+* lenovo/g505s                  4.4-1739
+* lenovo/x201                   4.4-1886
+* lenovo/x220                   4.4-1746 / 4.5-17
+
+coreboot statistics
+-------------------
+* Total Commits:            1889
+* Average Commits per day: 10.92
+* Total authors:             119
+* New authors:                47
+* Total Reviewers:            67
+* Total Submitters:           19
+* Total lines added:      164950
+* Total lines removed:   -182737
+* Total difference:       -17787
diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md
new file mode 100644
index 0000000..f6c29c6
--- /dev/null
+++ b/Documentation/releases/coreboot-4.6-relnotes.md
@@ -0,0 +1,486 @@
+Announcing coreboot 4.6
+=======================
+
+We are happy to announce the April 2017 release of coreboot, version
+4.6.
+
+The 4.6 release covers commit e74f5eaa to commit db508565
+
+Since the last release in October 2016, the coreboot project had 1708
+commits by 121 authors. The release tarballs and gpg signatures are
+available in the usual place at https://www.coreboot.org/downloads
+
+There is a pgp signed 4.6 tag in the git repository, and a branch will
+be created as needed.
+
+Changes: Past, ongoing, and future
+----------------------------------
+
+### CBMEM console development and the Linux Kernel
+
+Our cbmem debug console was updated with some nice features. The cbmem
+console now persists between reboots and is able to be used on some
+platforms via late init. Also there is a new Linux kernel driver which
+removes the need for the old cbmem tool to read from the cbmem area. You
+can find the patch here https://patchwork.kernel.org/patch/9641997/ and
+it can be enabled via GOOGLE_MEMCONSOLE_COREBOOT kconfig option in your
+kernel - Note that this name may change going forward.
+
+### Critical bugs in TPM 1.2 support
+
+coreboot currently has issues with the TPM 1.2 LPC driver
+implementation. This leads to a misbehavior in SeaBIOS where the TPM
+gets temporarily deactivated. We plan to publish the bugfix release
+4.6.1 when we have these issues sorted out.
+
+### Native graphics and ram init improvements
+
+The native graphics was reworked a while ago and should finally support
+Windows. Numerous bug fixes and EDID support is also now available.
+Finally, the native ram initialization for sandybridge/ivybridge
+platforms got patched and supports more RAM modules.
+
+### New and fresh payloads
+
+SeaBIOS, FiLO, and iPXE were all recently updated to the latest
+versions. Https downloads are the default for all payloads now. We
+provide the libpayload project which is used for writing own payloads
+from scratch. The library is MOSTLY licensed under BSD and recently
+received new functionality in order to prepare for the upcoming
+replacement for the old nvramcui payload. This new payload is called
+cbui and is based on the nuklear graphics library including keyboard and
+mouse support. The cbui payload is currently expected to be merged into
+the main coreboot tree before the next release.  The upstream repository
+is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
+
+### UEFI support: A long road to go
+
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
+is open source and available at Github. Sadly it is not currently
+integrated into the coreboot build. This has several reasons:
+
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
+
+We started to make progress with the integration into our sources and
+the hope is that by the end of the summer, we finally support the EDK2
+payload out-of-the- box. See the current patch state at
+http://review.coreboot.org/#/c/15057/
+
+### Fighting blobs and proprietary HW components
+
+coreboot's ultimate goal would be to replace any closed source firmware
+stack with free software components. Unfortunately this is not always
+possible due to signed binaries such as the Intel ME firmware, the AMD
+PSP and microcode. Recently, a way was discovered to let the Intel ME
+run in a functional error state and reduce it from 1.5/5MB to 80KB. It's
+not perfect but it works from Nehalem up to Skylake based Intel systems.
+The tool is now integrated into the coreboot build system. The upstream
+repository is https://github.com/corna/me_cleaner
+
+Another ongoing improvement is the new utility blobtool. It is currently
+used for generating the flash descriptor and GbE configuration data on
+older mainboard which are known to be free software. It can easily be
+extended for different binaries with well-defined specifications.
+
+### Did you say Ada?
+
+coreboot now supports Ada, and a lot work was done integrating Ada into
+our toolchain. At the moment only the support for formal verification is
+missing and will be soon added. At that point, we can prove the absence
+of runtime errors in our Ada code. In short, everybody can start
+developing Ada code for our project.
+
+The existing Ada code which can be used from now on is another native
+graphics initialization which will replace in the long term the current
+implementation. The native graphics code supports all Intel platforms up
+to skylake. We offer support for HDMI, VGA, DVI and DP external
+interfaces as well and is ready to be integrated into our mainboard
+implementations.
+
+### Toolchain updates
+
+A new coreboot toolchain is out. The major toolchain change was going
+from GCC version 5.3.0 to 6.3.0. There were also minor version updates
+to GMP, MPFR, Binutils, GDB, IASL, and Clang.
+
+### Deprecation policy for boards
+
+Starting with this release there will be a policy for deprecating
+unmaintained boards. See the end of this announcement for details.
+
+Change Summary
+--------------
+
+Build system (20 commits)
+* Clean up Kconfig
+* Show more useful error messages
+
+Codebase cleanup (94 commits)
+* Many fixes for files to pass checkpatch. Lots more to do here.
+* Remove commented out code
+* Updates to transition away from device_t
+* Work to get rid of included C files
+
+Documentation (6 commits)
+* Start adding technotes/Design docs
+* Add Kconfig documentation
+
+ACPI & acpigen library
+* Add GPIO macros
+* Clean up and add more functions to ACPIGEN library
+
+EC (26 commits)
+* Add roda/it8518 embedded controller
+
+TPM (41 commits)
+* Cleanup
+* Update ACPI ASL, Runtime generate ACPI table for TPM driver
+* Make SPI TPM driver CAR-safe
+* Update TPM init sequence
+
+Devices (24 commits)
+* Add a new SPI device type
+* Allow devicetree accesses in postcar stage
+* PCIEXP_ASPM: Unify code with other PCI-e tuning
+
+Lib (28 commits)
+* Add option to use Ada code in ramstage
+* bootstate: add arch specific hook at coreboot exit
+* cbfs: Add API to locate a file from specific region
+* Add library to handle SPD data in CBFS or DIMM
+* Add region file support
+* Turn CBMEM console into a ring buffer that can persist across reboots
+
+Commonlib (11 commits)
+* Add xmalloc, xzmalloc and dma routines
+* Add input and output buffer helpers
+
+Drivers (29 commits)
+* i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdt
+* i2c/alps: Add support for ALPS Touchpad driver
+* i2c/generic: Add support for GPIO IRQ
+* i2c/generic: Enable support for adding PowerResource for device
+* i2c/hid: Add generic I2C HID driver
+* i2c/max98927: add i2c driver for Maxim 98927 codec
+* i2c/wacom_ts: Add support for WCOM touchscreen device driver
+* pc80/rtc: Check cmos checksum BEFORE reading cmos value
+* regulator: Add driver for handling GPIO-based fixed regulator
+* storage: Add SD/MMC/eMMC driver based upon depthcharge
+
+SPI interface
+* Significant cleanup and refactoring
+
+Include (17 commits)
+* cpu/intel: Add MSR to support enabling turbo frequency
+* elog: Add all EC event codes
+
+SuperIO (12 commits)
+* Updates for ITE SIOs
+* Add 2 new chips
+* Consolidate code to use common routines
+
+Vboot (23 commits)
+* Add support for recovery hash space in TPM
+
+RISC-V (25 commits)
+* Add lowRISC System On Chip support
+* Cbmem patches, move to common architectural code
+
+ARM (16 commits)
+* Init new serial struct variables for samsung exynos5420 & allwinner
+  a10
+* Fix verstage to use proper assembly versions of mem*()
+
+RockChip RK3399 & platforms (46 commits)
+* Memory, I2C, USB, SD & Display fixes
+
+X86 Intel (193 commits)
+* Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and
+  3.
+* cpu/intel/common: Add/Use common function to set virtualization
+* drivers/intel/fsp1_1: Fix boot failure for non-verstage case
+* drivers/intel/fsp2_0: Reset on invalid stage cache.
+* drivers/intel/gma: Add textmode using libgfxinit & use scaling to
+  simplify  config
+* drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generator
+* broadwell_de: Add SMM code
+* intelblocks/msr: Move intel x86 MSR definition into common location
+* intel/broadwell: Use the correct SATA port config for setting IOBP
+  register
+* intel/wifi: Create ACPI objects for wifi SAR configuration
+* lynxpoint bd82x6x: Enable PCI-to-PCI bridge
+* mrc: Add support for separate training cache in recovery mode
+* nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual
+  Channel
+* nb/i945/raminit: Add fixes for 800MHz & 1067MHz FSB CPUs
+* nb/intel/gm45: Fix panel-power-sequence clock divisor
+* nb/intel/i945: Fix PEG port on 945gc & sdram_enhanced_addressing for
+  channel1
+* nb/intel/pineview: Move to early cbmem
+* nb/pineview/raminit: Skip Jedec init on resume, fix hot reset path
+* nb/intel/sandybridge/gma: Always initialize DP buffer translation
+* sb/ich7: Use common/gpio.h to set up GPIOs
+* sb/intel/bd82x6x: Add TCO_Lock in finalize step
+* sb/intel/common/gpio: Support ICH9M and prior
+* sb/intel/i82801gx: Add i2c_block_read to smbus.h
+
+sandybridge/raminit
+* Fix CAS Write Latency, disable_channel, normalize_training & odt stretch
+* Separate Sandybridge and Ivybridge
+* Reset internal state on fallback attempts
+* Find CMD rate per channel
+
+soc/intel/common
+* Add common routines for HECI, ITSS, PCR, RTC, systemagent, UART, XHCI,
+& LPSS
+* Save Memory DIMM Information in SMBIOS table
+
+Apollolake (183 commits)
+* Switch to common routines for LPSS, RTC, ITSS, UART, XHCI, & PCR
+* Enable turbo
+* Add save/restore variable MRC cache
+* Allow ApolloLake SoC to use FSP CAR Init
+* Allow USB2 eye pattern configuration in devicetree
+
+Quark & platforms (14 commits)
+* Fix I2c & Serial port config
+* Add vboot support
+
+ga-g41m-es2l, x4x northbridge & LGA775 (23 commits)
+* Memory fixes
+* Add S3 suspend/resume
+
+Skylake / Kabylake (208 commits)
+* Add devicetree settings for acoustic noise mitigation
+* Perform CPU MP Init before FSP-S Init
+* Add support for GSPI controller & add GSPI controller get_config
+support
+* Enable Systemagent IMGU
+* Add USB Port Over Current support & Expand USB OC pins support PCH-H
+* Extract DIMM Information from FSP MEM INFO HOB
+* Add support for eSPI SMI events
+* Update ACPI & various methods
+
+X86 amd (116 commits)
+* ACPI S3: Remove HIGH_MEMORY_SAVE where possible
+* AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
+* binaryPI platforms: Drop ACPI S3 support
+* sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used
+* southbridge/amd: Add LPC bridge acpi path for Family14 and SB800
+* arch/x86: remove CAR global migration when postcar stage is used
+* x86/acpi: Add VFCT table
+
+AMD: vendorcode, AGESA, binaryPI (72 commits)
+* Cleanup & consolidate duplicate code
+* Fork for new cache-as-ram init code & Fix binaryPI cache-as-ram
+* Refactor S3 support functions and Delay ACPI S3 backup until ramstage
+  loader
+
+amd/mct:
+* Fix CsMux45 configuration, maximum read latency, & DQ mask calculation
+
+Mainboards (198 commits)
+* asus/f2a85-m_le: Activate IOMMU support
+* lenovo/h8: Add USB Always On
+* google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panel
+* google/parrot: Fix keyboard interrupts, DSDT
+* google/veyron: Work around RAM code strapping error
+* lenovo/t400: Rewrite dock from t60
+* intel/d510mo: enable ACPI resume from S3
+* intel/d945gclf: Fix resume from S3 suspend
+* lenovo/t400: Implement hybrid graphic in romstage
+* Enable libgfxinit on lenovo/t420 & x230, kontron/ktqm77, google/slippy
+* lenovo/x60,t60: Move EC CMOS parameters in checksummed space
+* mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing
+* mc_tcu3: Swap LVDS even and odd lanes for a certain hardware
+* purism/librem13: Enable support for M.2 NVMe & Fix M.2 issues
+
+Payloads (53 commits)
+* Update FILO, SeaBIOS, & iPXE versions
+* Many libpayload fixes and updates
+
+Toolchain (19 commits)
+* Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM
+
+Utilities: (145 commits)
+* abuild: Build saved config files and print failed builds at the end
+* autoport: Create superiotool logs and fix romstage generator
+* board-status: Update bucketize script and add README file
+* cbfstool: Add cbfs-compression-tool and enable adding precompressed
+  files
+* cbmem: Add custom aligned memcpy() implementation
+* ectool: Fix timeout on sending EC command and support OpenBSD
+* ifdtool: Fix ICH Gbe unlock
+* intelmetool: Add support for Wildcat Point LP, fix segfault on edge
+  cases
+* inteltool: Add support for CH6-10, ICH10, Wildcat Point-LP and fix ICH
+SPIBAR
+* sconfig: Add a new SPI device type
+* superiotool: Add new chips - IT8783E/F, W83627DHG, W83627EHG, F71808A
+
+Changes in chips
+----------------
+
+Added 1 processor & northbridge:
+* amd/pi/00670F00
+
+Added 1 soc:
+* lowrisc/lowrisc
+
+Removed 1 northbridge:
+* intel/e7501
+
+Added 2 sios:
+* fintek/f71808a
+* ite/it8783ef
+
+Mainboard changes
+-----------------
+
+Added 52 mainboards and variants:
+* AMD Gardenia - AMD Stoney Ridge
+* Asus F2A85_M_PRO - AMD Family 15h Trinity
+* Asus P5GC_MX - Intel Socket LGA775
+* Gigabyte GA_945GCM_S2L & GA_945GCM_S2C variant - Intel Socket LGA775
+* Google Auron variants: Yuna, Gandof, Lulu - Intel Broadwell
+* Google Beltino variants: McCloud, Monroe, Tricky, Zako - Intel Haswell
+* Google Eve - Intel Kabylake
+* Google Fizz - Intel Kabylake
+* Google Gru variants: Bob, Scarlet - RockChip RK3399
+* Google Oak variants: Hana, Rowan - MediaTek MT8173
+* Google Poppy & Soraka variant - Intel Kabylake
+* Google Rambi variants: Banjo, Candy, Clapper, Glimmer, Gnawty, Heli,
+  Kip, Orco, Quawks, Squawks, Sumo, Swanky, & Winky - Intel Baytrail
+* Google Reef variants: Sand, Snappy, Nasher - Intel Apollolake
+* Google Slippy variants: Leon, Wolf - Intel Haswell
+* Intel KBLRVP3 & KBLRVP7 - Intel Kabylake
+* Intel LEAFHILL - Intel Apollolake
+* Intel MINNOW3 - Intel Apollolake
+* Lenovo L520: Intel Sandybridge
+* Lenovo S230U: Intel Ivybridge
+* Lenovo X1 Carbon GEN1 - Intel Sandybridge
+* lowRISC NEXYS4DDR - RiscV
+* MSI MS7721 - AMD Bulldozer
+* PC Engines APU2 - AMD Jaguar
+* RODA RV11 & RW11 variant - Intel Ivybridge
+* Sapphire Pure Platinum H61 - Intel Socket LGA1155
+* Siemens MC_APL1 - Intel Apollolake
+
+Removed 10 mainboard variants:
+* Google Auron (Still available as a base-board for variants)
+* Google Veyron Chromeboxes: Brain, Danger, Emile, Romy
+* Google Veyron Test Projects: Gus, Nicky, Pinky, Shark, Thea
+
+Utilities
+---------
+
+Added 2 new utilities:
+* blobtool
+* me_cleaner
+
+Submodules
+----------
+
+Updated 5 submodules
+* 3rdparty/blobs (10 commits)
+* 3rdparty/arm-trusted-firmware (172 commits)
+* 3rdparty/vboot (158 commits)
+* 3rdparty/chromeec/ (810 commits)
+* util/nvidia/cbootimage (2 commits)
+
+Tested boards
+-------------
+
+The following boards were tested recently:
+* emulation qemu-q35                    4.6-1
+* asus kgpe-d16                         4.6-1
+* asus kfsn4-dre                        4.6-1
+* asus p5gc-mx                          4.6-1
+* lenovo x60                            4.5-1681 / 4.6-7
+* lenovo x230                           4.5-1674 / 4.6-27
+* asrock e350m1                         4.5-1662 / 4.6-7
+* lenovo t420                           4.5-1640
+* lenovo x200                           4.5-1598 / 4.6-33
+* sapphire pureplatinumh61              4.5-1575
+* gigabyte ga-945gcm-s2l                4.5-1568
+* lenovo t400                           4.5-1564
+* lenovo t60                            4.5-1559
+* gigabyte m57sli                       4.5-1526
+* purism librem13                       4.5-1503
+* gigabyte ga-g41m-es2l                 4.5-1444
+* google slippy                         4.5-1441
+* intel d510mo                          4.5-1341
+
+coreboot statistics from e74f5eaa43 to db508565d2
+-------------------------------------------------
+
+* Total Commits: 1708
+* Average Commits per day: 8.75
+* Total authors: 121
+* New authors: 34
+* Total Reviewers: 72
+* Total Submitters: 19
+* Total lines added: 177576
+* Total lines removed: - 107460
+* Total difference: 70116
+
+Code removal after the 4.6 release
+----------------------------------
+
+The only platform currently scheduled for removal is the
+bifferos/bifferboard & soc/rdc/r8610. This platform is one of two that
+still uses romcc to compile romstage and doesn't have cache-as-ram in
+romstage - the others were all removed long ago. Additionally, it seems
+to be impossible to buy, so as far as it can be determined, no testing
+has been done recently.
+
+Code removal after the 4.7 release
+----------------------------------
+
+One of the things that the coreboot project has struggled with is how to
+maintain the older platforms while still moving the rest of the
+platforms forward. Currently there are numerous platforms in the
+codebase which have not been well maintained.
+
+Starting with the 4.7 release in October, the coreboot leadership is
+going to set standards that platforms are expected to meet to remain in
+the active codebase. These will generally be announced 3 - 6 months in
+advance to give time to get changes in. The expectation is not
+necessarily even that all work to meet the goal will be completed, but
+it is expected that a reasonable effort has started to meet the goal at
+the time of the release. Regardless of the work that's been done,
+platforms which have not met the goal by the following release will be
+removed.
+
+The next expectation that will need to be met for all platforms is cbmem
+in romstage. This currently affects numerous platforms, including most,
+if not all of AMD's platforms. Work to update many of these platforms
+has started, but there are others that have not made any progress
+towards this goal. A list of the platforms that are affected by this
+will be sent to the mailing list shortly.
+
+Code removal after the 4.8 release
+----------------------------------
+
+To further clean things up, starting with the 4.8 release, any platform
+that does not have a successful boot logged in the board_status repo in
+the previous year (that is, within the previous two releases) will be
+removed from the maintained coreboot codebase. Chips that do not have
+any associated boards will also be removed. These platforms will be
+announced before the release so that there is time for people to test if
+desired.
+
+This is not meant to be a high bar, but as a measure to clean up the
+codebase and eliminate boards and chips that are actually no longer
+being used. The cleanup will happen just after the release, so the
+removed platforms will still be available in the release branch if
+desired. If there is still interest, developers can bring back old chips
+and boards by porting them to the new tree (and bringing them to current
+standards).
+
+This gives everyone until April 2018 to get any boards that they care
+about tested before the first removal.
+
+All the code removal information will also be sent to the mailing list
+along with additional details.
diff --git a/Documentation/releases/coreboot-4.7-relnotes.md b/Documentation/releases/coreboot-4.7-relnotes.md
new file mode 100644
index 0000000..ac9d817
--- /dev/null
+++ b/Documentation/releases/coreboot-4.7-relnotes.md
@@ -0,0 +1,197 @@
+coreboot 4.7 release notes
+==========================
+
+The 4.7 release covers commit 0a4a4f7ae4 to commit fd470f7163
+Since the last release in April 2017, the coreboot project had 2573 commits by 150 authors.
+
+There is a pgp signed 4.7 tag in the git repository, and a branch will be created as needed.
+
+
+New chipsets
+------------
+
+* AMD Stoney Ridge
+* Intel i82801jx Southbridge (ICH10)
+* Intel Denverton and Denverton-NS
+* Work has started on Intel Cannon Lake
+
+Added 47 mainboards & variants:
+-------------------
+
+* Acer Chromebook 14 CB3-431 [google/edgar]           Intel Braswell
+* Acer Chromebook 15 CB3-532 [google/banon]           Intel Braswell
+* Acer Chromebook N7 C731 [google/relm]               Intel Braswell
+* ASRock B75 Pro3-M                                   Intel Ivy Bridge
+* ASRock G41C-GS R2.0                                 Intel G41/ICH7
+* Asus AM1I-A                                         AMD Kabini
+* Asus Chromebook C202SA/C300SA/C301SA (google/terra) Intel Braswell
+* Biostar A68N-5200                                   AMD Kabini
+* Compulab Intense-PC                                 Intel Ivy Bridge
+* Dell Chromebook 11 3180/3189 (google/kefka)         Intel Braswell
+* Foxconn G41S-K                                      Intel G41/ICH7
+* Google Coral                                        Intel Apollo Lake
+* Google Grunt                                        AMD Stoney Ridge
+* Google Kahlee                                       AMD Stoney Ridge
+* Google Meowth                                       Intel Cannon Lake
+* Google Nami                                         Intel Kaby Lake
+* Google Nautilus                                     Intel Kaby Lake
+* Google Nefario                                      Rockchip RK3399
+* Google Rainier                                      Rockchip RK3399
+* Google Soraka                                       Intel Kaby Lake
+* Google Zoombini                                     Intel Cannon Lake
+* HP Chromebook 11 G5 (google/setzer)                 Intel Braswell
+* HP EliteBook 2570p                                  Intel Ivy Bridge
+* HP EliteBook 2760p                                  Intel Sandy Bridge
+* HP EliteBook 8460p                                  Intel Sandy Bridge
+* HP EliteBook 8470p                                  Intel Ivy Bridge
+* HP EliteBook Revolve 810 G1                         Intel Ivy Bridge
+* Intel Cannnlake RVPU                                Intel Cannon Lake
+* Intel Cannonlake RVPY                               Intel Cannon Lake
+* Intel D410PT                                        Intel Atom D410
+* Intel DG43GT                                        Intel G43/ICH10
+* Intel GLKRVP                                        Intel Gemini Lake
+* Intel Harcuvar                                      Intel Denverton
+* Intel NUC DCP847SKE                                 Intel Sandy Bridge
+* Intel Saddle Brook reference board                  Intel Skylake
+* Lenovo N22/N42 Chromebook (google/reks)             Intel Braswell
+* Lenovo T430                                         Intel Ivy Bridge
+* Lenovo Thinkpad 11e/Yoga Chromebook G3
+  (google/ultima)                                     Intel Braswell
+* Lenovo ThinkPad X131e                               Intel Sandy Bridge
+* Lenovo Z61T                                         Intel i945/ICH7
+* PC Engines APU3                                     AMD Steppe Eagle
+* PC Engines APU4                                     AMD Steppe Eagle
+* PC Engines APU5                                     AMD Steppe Eagle
+* Purism Librem 13 v2                                 Intel Skylake
+* Purism Librem 15 v3                                 Intel Skylake
+* Samsung Chromebook 3 (google/celes)                 Intel Braswell
+* White label Chromebook (google/wizpig)              Intel Braswell
+* WinNET G170                                         VIA CN700
+
+Removed 2 mainboards
+--------------
+
+* Biferos Bifferboard
+* Google Cosmos
+
+New Embedded Controller
+-----------------------
+
+* KBC1126 used in HP EliteBooks
+
+General changes
+---------------
+
+* Integrate me_cleaner
+* Add flashconsole implementation
+* Build Tianocore UEFI payload from upstream source
+* Remove CMOS NVRAM configurable baud rates
+* A common mrc_cache driver to store romstage settings in SPI flash
+
+Google ChromeOS devices:
+------------------------
+
+* Add ACPI USB port definitions for many boards
+* Fix preprocessor guards for LPC TPM
+* Remove non-existent IRQ for LPC TPM
+* Fix LED control for mccloud
+* Enable keyboard backlight at boot on equipped boards
+* Fix ACPI data for non-google EC's to improve Windows compatibility
+* Add missing SPD files for chell, fixing support for > 4GB boards
+
+Lenovo Thinkpads:
+-----------------
+
+* Add support for passive cooling
+* Add ACPI fan control
+* Add BDC detection and power saving
+* Unify hybrid graphics and improved power saving
+
+Intel Braswell:
+---------------
+
+* Add support for all outstanding Braswell ChromeOS devices
+* Update FSP 1.1 header to v1.1.7.0
+* Adjust FSP header revision check to be less stringent
+* Upstream numerous commits from Chromium tree
+* Fix ACPI scope for I2C devices
+* Fix SPI write after flash lockdown set
+
+Legacy Intel Boards:
+--------------------
+
+* Unify Intel VBT handling
+* Add support for loading external VBT
+* Provide the VBT through Intel OpRegion method on all platforms
+* Fix low memory corruption on S3 resume path
+
+Intel Sandy Bridge:
+------------------
+
+* Add a Kconfig option to ignore XMP max DIMMs
+* Add Kconfig option for max. DRAM frequency fuses
+* Advertise correct DRAM frequency on Ivy Bridge
+* Improve CAS/frequency selection
+* Use command rate 2T on channels with two DIMMs installed for improved
+stability
+
+Intel X4X:
+----------
+
+* Fix booting with FSB800 DDR667 combination
+* Rework ram DQS receiver enable training sequence
+* Rework and fix SPD reading and decoding
+* Allow external GPU to take VGA cycles
+
+Intel GM45:
+-----------
+
+* Improve compatibility with mixed DIMMs
+* Add romstage timings
+* Set the display backlight PWM correctly
+
+Intel Pineview:
+---------------
+
+* Enable remapping of memory to allow for 4G or more memory
+
+Intel I440BX
+------------
+
+* Implement early CBMEM support
+* Fix RAM init programming
+
+AMD AGESA
+---------
+
+* Move boards to early CBMEM and add timestamps
+* Refactor boards away from using agesawrapper
+* Wipe unused sources under vendorcode
+* Re-enable ACPI S3 after fixing low memory corruptions
+
+AMD binaryPI
+------------
+
+* Move boards to early CBMEM
+* Continue work on cleaning up headers
+
+libgfxinit
+----------
+
+* Support new hardware: Broxton/APL (DP and HDMI only), Skylake
+* Handle framebuffer mapping in the library
+* Make DP training more compatible and tolerant
+* Enhance compatibility for VGA adaptors
+
+intelmetool
+-----------
+
+* Add support for Sunrise Point LP
+* Add Intel Boot Guard detection
+
+Toolchain
+---------
+
+* buildgcc now verifies downloaded files against hashes
+* Improve GNAT detection
+* Update binutils to 2.29.1
diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md
new file mode 100644
index 0000000..8a6ab96
--- /dev/null
+++ b/Documentation/releases/coreboot-4.8.1-relnotes.md
@@ -0,0 +1,179 @@
+coreboot 4.8 & 4.8.1 release notes
+==================================
+
+The 4.8.1 release contains 2 commits: 5f0b80b880 and 6794ce02d4.  This
+minor release fixes an issue with adding payloads. The 4.8 release
+covers commit 6dd2f69878 to commit ebdeb4d07d
+
+Since the last release, the coreboot project had 1198 commits by 124
+authors.
+
+There are PGP signed 4.8 and 4.8.1 tags in the git repository.  A branch
+for 4.8 releases (4.8_branch) has been created.
+
+A big thank you to everyone involved in making this release happen. We
+couldn't have done this without the 35 new commit authors, the
+experienced developers, the many reviewers, documentation writers and
+the fantastic community supporting users on both the mailing list and
+the IRC channel.
+
+In general, this has been a calm release cycle. Several old devices were
+removed from the master branch early in the release, as they hinder
+development and nobody stepped up doing the porting effort or was
+willing to test coreboot on them. If there is the desire to get a board
+back, it isn't lost as it’s still in the git history.
+
+Intel i945 platform
+-------------------
+* On Intel 945 devices, native graphics initialization is now skipped
+saving around 100 ms during resume from S3. The OS drivers need to be
+able to handle that. Linux’ i915 driver is able to handle it, but not
+the frame buffer driver.
+
+AMD Stoney Ridge
+----------------------------------
+* Significant cleanup from older AGESA based platforms
+* Fixes to get S3 working
+* Updates to GPIO code to match other modern coreboot chips
+* AGESA interface cleanup - Use native coreboot functions when
+possible
+
+Lenovo mainboards
+-----------------
+* Started integration of VBT (Video Bios Table) binary files to
+support native graphics initialisation
+
+Internal changes
+----------------
+* Rename of payload type 'payload' to 'simple_elf'
+* Progress in removing typedef device_t
+* Migrated all Intel platforms to a common VBT codebase
+* Ongoing cleanup of whitespace, spelling and formatting
+* Support for PCI in ramstage on non-x86
+* Ongoing Intel platform code deduplication
+
+Console changes
+---------------
+* Reduce default loglevel to DEBUG
+* Introduce a way for mainboard to override the loglevel
+* Restrict console messages to after console initialization
+
+Fixed Bugs
+----------
+* qemu-i440fx: Fix ACPI checksum corruption
+* intelmetool: Fix crash, support ME11+ platforms, fix bootguard
+detection
+* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 (https://github.com/nccgroup/TPMGenie)
+* asrock/b75pro3-m: Fixed HDMI
+* Intel/ibexpeak: Fix missing ACPI PIRQ entries
+* Intel/nehalem: Fix freeze during chipset lockdown
+
+Payloads
+--------
+* Bumped SeaBIOS to 1.11.1
+* Improved TianoCore integration
+
+Security
+--------
+* Start of refactoring the TPM software stack
+* Introduced coreboot security section in kconfig
+* VBoot & TPM code moved into src/security
+
+Intelmetool
+-----------
+* Add Intel Boot Guard status support
+
+Documentation
+-------------
+* Switch from Hugo to Sphinx for the Documentation
+* Working on markdown documentation for https://doc.coreboot.org
+
+Added 17 mainboards
+-------------------
+* Asus MAXIMUS_IV_GENE_Z                               Intel Sandybridge
+* Google ATLAS                                         Intel Kabylake
+* Google BIP                                           Intel Geminilake
+* Google CHEZA                                         Qualcomm SDM845
+* Google NOCTURNE                                      Intel Kabylake
+* Google OCTOPUS                                       Intel Geminilake
+* Google PHASER                                        Intel Geminilake
+* Google YORP                                          Intel Geminilake
+* HP 8770W                                             Intel Ivybridge
+* HP FOLIO_9470M                                       Intel Ivybridge
+* Intel KBLRVP8                                        Intel Skylake
+* Lenovo W520                                          Intel Sandybridge
+* OCP MONOLAKE                                         Intel Broadwell DE
+* OCP WEDGE100S                                        Intel Broadwell DE
+* Purism Librem 15 v2                                  Intel Broadwell
+* Scaleway TAGADA                                      Intel Denverton
+* SiFive HIFIVE_UNLEASHED                              SiFive FU540
+
+Removed 39 mainboards
+---------------------
+* Abit BE6_II_V2_0
+* AMD DINAR
+* AMD RUMBA
+* Asus DSBF
+* Asus MEW_AM
+* Asus MEW_VM
+* A-trend ATC_6220
+* A-trend ATC_6240
+* AZZA PT_6IBD
+* Biostar M6TBA
+* Compaq DESKPRO_EN_SFF_P600
+* DMP EX
+* ECS P6IWP_FE
+* Gigabyte GA_6BXC
+* Gigabyte GA_6BXE
+* HP E_VECTRA_P2706T
+* Intel D810E2CB
+* Intel EAGLEHEIGHTS
+* Intel MTARVON
+* Intel TRUXTON
+* Iwave RAINBOW_G6
+* Lanner EM8510
+* Lippert FRONTRUNNER
+* Mitac 6513WU
+* MSI MS_6119
+* MSI MS_6147
+* MSI MS_6156
+* MSI MS_6178
+* NEC POWERMATE_2000
+* Nokia IP530
+* RCA RM4100
+* Soyo SY_6BA_PLUS_III
+* Supermicro H8QGI
+* Supermicro H8SCM
+* Supermicro X7DB8
+* Thomson IP1000
+* Tyan S1846
+* Tyan S8226
+* Wyse S50
+
+Added 2 socs
+------------
+* Qualcomm sdm845
+* SiFive fu540
+
+Removed 2 socs
+--------------
+* DMP vortex86ex
+* Intel sch
+
+Removed 5 processors
+--------------------
+* AMD agesa-family15
+* AMD geode-gx2
+* Intel ep80579
+* Intel model-f0x
+* Intel model-f1x
+
+Statistics
+----------
+* Total commits: 1198
+* Average Commits per day: 9.85
+* Total authors: 124
+* New authors: 35
+* Total lines added: 386113
+* Total lines removed: 291201
+* Total lines difference: 94912
diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md
new file mode 100644
index 0000000..788d695
--- /dev/null
+++ b/Documentation/releases/coreboot-4.9-relnotes.md
@@ -0,0 +1,23 @@
+coreboot 4.9 release notes
+==========================
+
+The 4.9 release is planned for November 2018
+
+Update this document with changes that should be in the release
+notes.
+* Please use Markdown.
+* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md)
+ release notes for the general format.
+* The chip and board additions and removals will be updated right
+before the release, so those do not need to be added.
+
+
+
+General changes
+---------------
+
+
+Toolchain
+---------
+
+* Update IASL to version 10280531
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
new file mode 100644
index 0000000..fd95fd7
--- /dev/null
+++ b/Documentation/releases/index.md
@@ -0,0 +1,16 @@
+Release notes for previous releases
+===================================
+
+### * [4.1 - July 2015](coreboot-4.1-relnotes.md)
+### * [4.2 - October 2015](coreboot-4.2-relnotes.md)
+### * [4.3 - January 2016](coreboot-4.3-relnotes.md)
+### * [4.4 - May 2016](coreboot-4.4-relnotes.md)
+### * [4.5 - October 2016](coreboot-4.5-relnotes.md)
+### * [4.6 - April 2017](coreboot-4.6-relnotes.md)
+### * [4.7 - January 2018](coreboot-4.7-relnotes.md)
+### * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+
+Upcoming release
+----------------
+### * [4.9 - November 2018](coreboot-4.9-relnotes.md)
+Please add to the release notes as changes are added: