tree 8fbe42372b8ffda525e21f530e2c62ccc368d557
parent 57d4bc63f03664240ed4d9585c288ac8e455ca4b
author Werner Zeh <werner.zeh@siemens.com> 1637044304 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1637159207 +0000

drivers/siemens/nc_fpga: Add POST code over PCI

So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.

Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>