sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 30a34f7..766ed43 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -670,20 +670,22 @@
/* Set EOI forwarding disable. */
pci_or_config32(dev, 0xd4, 1 << 1);
- /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- if (CONFIG(PCIEXP_AER))
- pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
- else
- pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
+ /* Set AER Extended Cap ID to 01h */
+ u32 aech = CONFIG(PCIEXP_AER) ? 0x10001 : 0;
- /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
- if (CONFIG(PCIEXP_L1_SUB_STATE))
- pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
- else
- pci_update_config32(dev, 0x200, ~0xfffff, 0);
-
+ /* For PCH-LP, set Next Cap Pointer to 200h. */
if (is_lp)
- pci_or_config32(dev, 0x100, 1 << 29);
+ aech |= 1 << 29;
+
+ pci_update_config32(dev, 0x100, ~0xfffff, aech);
+
+ if (is_lp) {
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
+ if (CONFIG(PCIEXP_L1_SUB_STATE))
+ pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
+ else
+ pci_update_config32(dev, 0x200, ~0xfffff, 0);
+ }
/* Read and write back write-once capability registers. */
pci_update_config32(dev, 0x34, ~0, 0);