soc/amd: commonize PCI root IOAPIC initialization
Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.
Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c
new file mode 100644
index 0000000..cdeb532
--- /dev/null
+++ b/src/soc/amd/common/block/root_complex/ioapic.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/ioapic.h>
+#include <amdblocks/root_complex.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/resource.h>
+#include <types.h>
+
+void amd_pci_domain_init(struct device *domain)
+{
+ struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+ if (!res)
+ return;
+
+ register_new_ioapic((void *)(uintptr_t)res->base);
+}