tree 1e846c4c57712866a90f7a024c842a456392c3b3
parent 7ec4671f81c3a5fab33950f8635912f1a549323e
author Raymond Chung <raymondchung@ami.corp-partner.google.com> 1666666869 +0800
committer Werner Zeh <werner.zeh@siemens.com> 1666860060 +0000

mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave

The brask DDR4 is set to interleave, due to the limited number of
gaelin PCB layers and the traces need to be smooth,
we will use non-interleave for gaelin DDR4.

BUG=b:255399229, b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and pass MRC memory training

Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>