commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c
index 93590a1..237360e 100644
--- a/util/cbfstool/eventlog.c
+++ b/util/cbfstool/eventlog.c
@@ -369,59 +369,59 @@
{0, NULL},
};
static const struct valstr coreboot_post_codes[] = {
- {POST_RESET_VECTOR_CORRECT, "Reset Vector Correct"},
- {POST_ENTER_PROTECTED_MODE, "Enter Protected Mode"},
- {POST_PREPARE_RAMSTAGE, "Prepare RAM stage"},
- {POST_ENTRY_C_START, "RAM stage Start"},
- {POST_MEM_PREINIT_PREP_START, "Preparing memory init params"},
- {POST_MEM_PREINIT_PREP_END, "Memory init param preparation complete"},
- {POST_CONSOLE_READY, "Console is ready"},
- {POST_CONSOLE_BOOT_MSG, "Console Boot Message"},
- {POST_ENABLING_CACHE, "Before Enabling Cache"},
- {POST_PRE_HARDWAREMAIN, "Before Hardware Main"},
- {POST_ENTRY_HARDWAREMAIN, "First call in Hardware Main"},
- {POST_BS_PRE_DEVICE, "Before Device Probe"},
- {POST_BS_DEV_INIT_CHIPS, "Initialize Chips"},
- {POST_BS_DEV_ENUMERATE, "Device Enumerate"},
- {POST_BS_DEV_RESOURCES, "Device Resource Allocation"},
- {POST_BS_DEV_ENABLE, "Device Enable"},
- {POST_BS_DEV_INIT, "Device Initialize"},
- {POST_BS_POST_DEVICE, "After Device Probe"},
- {POST_BS_OS_RESUME_CHECK, "OS Resume Check"},
- {POST_BS_OS_RESUME, "OS Resume"},
- {POST_BS_WRITE_TABLES, "Write Tables"},
- {POST_BS_PAYLOAD_LOAD, "Load Payload"},
- {POST_BS_PAYLOAD_BOOT, "Boot Payload"},
- {POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, "FSP Notify Before End of Firmware"},
- {POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, "FSP Notify After End of Firmware"},
- {POST_FSP_TEMP_RAM_INIT, "FSP-T Enter"},
- {POST_FSP_TEMP_RAM_EXIT, "FSP-T Exit"},
- {POST_FSP_MEMORY_INIT, "FSP-M Enter"},
- {POST_FSP_SILICON_INIT, "FSP-S Enter"},
- {POST_FSP_NOTIFY_BEFORE_ENUMERATE, "FSP Notify Before Enumerate"},
- {POST_FSP_NOTIFY_BEFORE_FINALIZE, "FSP Notify Before Finalize"},
- {POST_OS_ENTER_PTS, "ACPI _PTS Method"},
- {POST_OS_ENTER_WAKE, "ACPI _WAK Method"},
- {POST_FSP_MEMORY_EXIT, "FSP-M Exit"},
- {POST_FSP_SILICON_EXIT, "FSP-S Exit"},
- {POST_FSP_MULTI_PHASE_SI_INIT_ENTRY, "FSP-S Init Enter"},
- {POST_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"},
- {POST_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"},
- {POST_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"},
- {POST_INVALID_ROM, "Invalid ROM"},
- {POST_INVALID_CBFS, "Invalid CBFS"},
- {POST_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"},
- {POST_RAM_FAILURE, "RAM Failure"},
- {POST_HW_INIT_FAILURE, "Hardware Init Failure"},
- {POST_VIDEO_FAILURE, "Video Failure"},
- {POST_TPM_FAILURE, "TPM Failure"},
- {POST_DEAD_CODE, "Dead Code"},
- {POST_RESUME_FAILURE, "Resume Failure"},
- {POST_JUMPING_TO_PAYLOAD, "Before Jump to Payload"},
- {POST_ENTER_ELF_BOOT, "Before ELF Boot"},
- {POST_OS_RESUME, "Before OS Resume"},
- {POST_OS_BOOT, "Before OS Boot"},
- {POST_DIE, "coreboot Dead"},
+ {POSTCODE_RESET_VECTOR_CORRECT, "Reset Vector Correct"},
+ {POSTCODE_ENTER_PROTECTED_MODE, "Enter Protected Mode"},
+ {POSTCODE_PREPARE_RAMSTAGE, "Prepare RAM stage"},
+ {POSTCODE_ENTRY_C_START, "RAM stage Start"},
+ {POSTCODE_MEM_PREINIT_PREP_START, "Preparing memory init params"},
+ {POSTCODE_MEM_PREINIT_PREP_END, "Memory init param preparation complete"},
+ {POSTCODE_CONSOLE_READY, "Console is ready"},
+ {POSTCODE_CONSOLE_BOOT_MSG, "Console Boot Message"},
+ {POSTCODE_ENABLING_CACHE, "Before Enabling Cache"},
+ {POSTCODE_PRE_HARDWAREMAIN, "Before Hardware Main"},
+ {POSTCODE_ENTRY_HARDWAREMAIN, "First call in Hardware Main"},
+ {POSTCODE_BS_PRE_DEVICE, "Before Device Probe"},
+ {POSTCODE_BS_DEV_INIT_CHIPS, "Initialize Chips"},
+ {POSTCODE_BS_DEV_ENUMERATE, "Device Enumerate"},
+ {POSTCODE_BS_DEV_RESOURCES, "Device Resource Allocation"},
+ {POSTCODE_BS_DEV_ENABLE, "Device Enable"},
+ {POSTCODE_BS_DEV_INIT, "Device Initialize"},
+ {POSTCODE_BS_POST_DEVICE, "After Device Probe"},
+ {POSTCODE_BS_OS_RESUME_CHECK, "OS Resume Check"},
+ {POSTCODE_BS_OS_RESUME, "OS Resume"},
+ {POSTCODE_BS_WRITE_TABLES, "Write Tables"},
+ {POSTCODE_BS_PAYLOAD_LOAD, "Load Payload"},
+ {POSTCODE_BS_PAYLOAD_BOOT, "Boot Payload"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, "FSP Notify Before End of Firmware"},
+ {POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, "FSP Notify After End of Firmware"},
+ {POSTCODE_FSP_TEMP_RAM_INIT, "FSP-T Enter"},
+ {POSTCODE_FSP_TEMP_RAM_EXIT, "FSP-T Exit"},
+ {POSTCODE_FSP_MEMORY_INIT, "FSP-M Enter"},
+ {POSTCODE_FSP_SILICON_INIT, "FSP-S Enter"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE, "FSP Notify Before Enumerate"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE, "FSP Notify Before Finalize"},
+ {POSTCODE_OS_ENTER_PTS, "ACPI _PTS Method"},
+ {POSTCODE_OS_ENTER_WAKE, "ACPI _WAK Method"},
+ {POSTCODE_FSP_MEMORY_EXIT, "FSP-M Exit"},
+ {POSTCODE_FSP_SILICON_EXIT, "FSP-S Exit"},
+ {POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY, "FSP-S Init Enter"},
+ {POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"},
+ {POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"},
+ {POSTCODE_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"},
+ {POSTCODE_INVALID_ROM, "Invalid ROM"},
+ {POSTCODE_INVALID_CBFS, "Invalid CBFS"},
+ {POSTCODE_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"},
+ {POSTCODE_RAM_FAILURE, "RAM Failure"},
+ {POSTCODE_HW_INIT_FAILURE, "Hardware Init Failure"},
+ {POSTCODE_VIDEO_FAILURE, "Video Failure"},
+ {POSTCODE_TPM_FAILURE, "TPM Failure"},
+ {POSTCODE_DEAD_CODE, "Dead Code"},
+ {POSTCODE_RESUME_FAILURE, "Resume Failure"},
+ {POSTCODE_JUMPING_TO_PAYLOAD, "Before Jump to Payload"},
+ {POSTCODE_ENTER_ELF_BOOT, "Before ELF Boot"},
+ {POSTCODE_OS_RESUME, "Before OS Resume"},
+ {POSTCODE_OS_BOOT, "Before OS Boot"},
+ {POSTCODE_DIE, "coreboot Dead"},
{0, NULL},
};
static const struct valstr mem_cache_slots[] = {