commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 9261d54..c1cf663 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -22,7 +22,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index b38ce80..372f515 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -48,7 +48,7 @@
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index e123c36..72d7788 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -63,6 +63,6 @@
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c
index a6d9a73..b81b9bc 100644
--- a/src/soc/amd/common/block/cpu/smm/finalize.c
+++ b/src/soc/amd/common/block/cpu/smm/finalize.c
@@ -20,7 +20,7 @@
acpi_enable_sci();
}
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 49cd11c..f780f21 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -25,7 +25,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c
index c742db0..5d6bb16 100644
--- a/src/soc/amd/mendocino/cpu.c
+++ b/src/soc/amd/mendocino/cpu.c
@@ -23,7 +23,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c
index 2c8f7713..1932777 100644
--- a/src/soc/amd/phoenix/cpu.c
+++ b/src/soc/amd/phoenix/cpu.c
@@ -25,7 +25,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c0b918e..be767dc 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -22,7 +22,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 3aedd0e..f2df3ce 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -24,7 +24,7 @@
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 2900045..460c8af 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -91,7 +91,7 @@
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 79614af..b64364b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -146,7 +146,7 @@
} else if (s3resume) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 20bb187..d71ac09 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -58,7 +58,7 @@
broadwell_pch_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index d088e51..c55e755 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -102,7 +102,7 @@
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 9df4ac3..837f157 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -84,7 +84,7 @@
pmc_base_reg = get_pmc_reg_base();
if (!pmc_base_reg)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Invalid PMC base address\n");
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index e45ae9a..ba7fc69 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -93,7 +93,7 @@
heci1_disable();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl
index 6a19792..8afb6ff 100644
--- a/src/soc/intel/common/acpi/platform.asl
+++ b/src/soc/intel/common/acpi/platform.asl
@@ -18,7 +18,7 @@
Method (_PTS, 1)
{
- DBG0 = POST_OS_ENTER_PTS
+ DBG0 = POSTCODE_OS_ENTER_PTS
If (CondRefOf (\_SB.PCI0.LPCB.EC0.PTS))
{
@@ -42,7 +42,7 @@
Method (_WAK, 1)
{
- DBG0 = POST_OS_ENTER_WAKE
+ DBG0 = POSTCODE_OS_ENTER_WAKE
If (CondRefOf (\_SB.PCI0.LPCB.EC0.WAK))
{
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index f2ae72c..5f6b6de 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -302,7 +302,7 @@
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 0126a12..7532c7d 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -20,7 +20,7 @@
.global cache_as_ram
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
movl $(CONFIG_FSP_T_LOCATION), %ebx
add $0x94, %ebx
@@ -99,7 +99,7 @@
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 81a5d34..f163e22 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -117,7 +117,7 @@
memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
if (!memory_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Graphic memory bar2 is not programmed!");
memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
@@ -140,7 +140,7 @@
if (!gtt_base) {
gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
if (!gtt_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"GTTMMADR is not programmed!");
}
return gtt_base;
diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c
index 537f388..70fbcaa 100644
--- a/src/soc/intel/common/block/p2sb/p2sblib.c
+++ b/src/soc/intel/common/block/p2sb/p2sblib.c
@@ -50,7 +50,7 @@
p2sb_dev_set_hide_bit(dev, 0);
if (p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to unhide the P2SB device!\n");
}
@@ -59,7 +59,7 @@
p2sb_dev_set_hide_bit(dev, 1);
if (!p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to hide the P2SB device!\n");
}
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 37d8579..2805011 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -62,7 +62,7 @@
struct pmc_resource_config *config = &pmc_cfg;
if (pmc_soc_get_resources(config) < 0)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to get PMC controller resource information!");
/* Get the normal PCI resources of this device. */
diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index d6ab737..275413b 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -49,7 +49,7 @@
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index 5665d75..6cff7a8 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -78,7 +78,7 @@
apm_control(APM_CNT_FINALIZE);
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index d249dd4..c2b1819 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -238,7 +238,7 @@
fsp_handle_reset(reset_status);
/* Control shouldn't return here */
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
}
diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c
index 6bd304c..a977b05 100644
--- a/src/soc/intel/meteorlake/finalize.c
+++ b/src/soc/intel/meteorlake/finalize.c
@@ -83,7 +83,7 @@
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index afa1c02..fd80aea 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -109,7 +109,7 @@
apm_control(APM_CNT_FINALIZE);
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
index 283efb5..cd02745 100644
--- a/src/soc/intel/tigerlake/finalize.c
+++ b/src/soc/intel/tigerlake/finalize.c
@@ -61,7 +61,7 @@
heci1_disable();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c
index 7830a4b..af630fe 100644
--- a/src/soc/intel/xeon_sp/finalize.c
+++ b/src/soc/intel/xeon_sp/finalize.c
@@ -70,7 +70,7 @@
lock_msr_ppin_ctl(NULL);
}
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
static void bios_done_finalize(void *unused)