commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 28422fb..ae4459a 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -119,7 +119,7 @@
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7adae9e..bf072fa 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -125,7 +125,7 @@
/* If MRC data is not found, we cannot continue S3 resume */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__);
system_reset();
}
@@ -157,7 +157,7 @@
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 3c0951d..ec93563 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -764,7 +764,7 @@
PRINT_DEBUG("Found DIMM in slot %d\n", i);
if (edo && sd) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"Mixing EDO/SDRAM unsupported!\n");
}
@@ -869,11 +869,11 @@
if (col == 4)
bpr |= 0xc0;
} else {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"# of banks of DIMM unsupported!\n");
}
if (dra == -1) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"Page size not supported!\n");
}
@@ -884,7 +884,7 @@
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"DIMMs smaller than 8MB per side "
"are not supported!\n");
}
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index a2a44c4..816fe31 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -168,7 +168,7 @@
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {