commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index 571feb4..17e0a69 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -34,7 +34,7 @@
movd %eax, %mm1
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/* Cache the rom and update the microcode */
cache_rom:
@@ -95,7 +95,7 @@
cmp $CONFIG_FSP_LOC, %eax
jbe halt1
- post_code(POST_FSP_TEMP_RAM_INIT)
+ post_code(POSTCODE_FSP_TEMP_RAM_INIT)
/* Calculate entry into FSP */
mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
@@ -222,7 +222,7 @@
#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
#endif
movl $LHLT_DELAY, %ecx
.Lhlt_Delay:
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index fc05b91..7455d30 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -29,7 +29,7 @@
void *fsp = cbfs_map("fsp.bin", NULL);
if (!fsp)
- die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");
+ die_with_post_code(POSTCODE_INVALID_CBFS, "Unable to locate fsp.bin");
/* This leaks a mapping which this code assumes is benign as
* the flash is memory mapped CPU's address space. */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 1c205ae..0d5faa8 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -135,10 +135,10 @@
if (phase == EnumInitPhaseReadyToBoot) {
timestamp_add_now(TS_FSP_FINALIZE_START);
- post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
+ post_code(POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE);
} else {
timestamp_add_now(TS_FSP_ENUMERATE_START);
- post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
+ post_code(POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE);
}
status = notify_phase_proc(¬ify_phase_params);
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 7da85d4..dd35b0f 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -50,7 +50,7 @@
* set to NULL. This indicates that the FSP code will use the UPD
* region in the FSP binary.
*/
- post_code(POST_MEM_PREINIT_PREP_START);
+ post_code(POSTCODE_MEM_PREINIT_PREP_START);
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
@@ -88,7 +88,7 @@
if (CONFIG(MMA))
setup_mma(&memory_init_params);
- post_code(POST_MEM_PREINIT_PREP_END);
+ post_code(POSTCODE_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (CONFIG(DISPLAY_UPD_DATA))
@@ -107,7 +107,7 @@
fsp_memory_init_params.HobListPtr);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- post_code(POST_FSP_MEMORY_INIT);
+ post_code(POSTCODE_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
mainboard_after_memory_init();
post_code(0x37);
@@ -115,7 +115,7 @@
printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
if (status != EFI_SUCCESS)
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"ERROR - FspMemoryInit failed to initialize memory!\n");
/* Locate the FSP reserved memory area */
@@ -172,7 +172,7 @@
}
if (hob_list_ptr == NULL)
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"ERROR - HOB pointer is NULL!\n");
/*
@@ -225,14 +225,14 @@
printk(BIOS_ERR,
"0x%08x: Chipset reserved bytes reported by FSP\n",
(unsigned int)delta_bytes);
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Please verify the chipset reserved size\n");
}
}
/* Verify the FSP 1.1 HOB interface */
if (fsp_verification_failure)
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"ERROR - coreboot's requirements not met by FSP binary!\n");
/* Locate the memory configuration data to speed up the next reboot */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index a4b17bd..200c89a 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -93,7 +93,7 @@
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n",
&silicon_init_params, fsp_silicon_init);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POSTCODE_FSP_SILICON_INIT);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 3f93f33..dc89064 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -56,7 +56,7 @@
printk(BIOS_DEBUG,
"No MRC cache "
"found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
/* FIXME: A "system" reset is likely enough: */
full_reset();
} else {
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 28e4d72..d6677b4 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -260,7 +260,7 @@
const struct fsp_header *hdr = &context->header;
const struct memranges *memmap = &context->memmap;
- post_code(POST_MEM_PREINIT_PREP_START);
+ post_code(POSTCODE_MEM_PREINIT_PREP_START);
if (CONFIG(MRC_CACHE_USING_MRC_VERSION))
version = fsp_mrc_version();
@@ -299,7 +299,7 @@
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, version,
memmap) != CB_SUCCESS)
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
/* Early caching of RAMTOP region if valid mrc cache data is found */
@@ -324,7 +324,7 @@
if (CONFIG(MMA))
setup_mma(&fspm_upd.FspmConfig);
- post_code(POST_MEM_PREINIT_PREP_END);
+ post_code(POSTCODE_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset);
@@ -332,7 +332,7 @@
/* FSP disables the interrupt handler so remove debug exceptions temporarily */
null_breakpoint_disable();
- post_code(POST_FSP_MEMORY_INIT);
+ post_code(POSTCODE_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
status = protected_mode_call_2arg(fsp_raminit,
@@ -342,13 +342,13 @@
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
null_breakpoint_init();
- post_code(POST_FSP_MEMORY_EXIT);
+ post_code(POSTCODE_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
/* Handle any errors returned by FspMemoryInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"FspMemoryInit returned with error 0x%08x!\n", status);
}
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 44e8795..22bbf53 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -22,24 +22,24 @@
{
.notify_phase = AFTER_PCI_ENUM,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE,
.timestamp_before = TS_FSP_ENUMERATE_START,
.timestamp_after = TS_FSP_ENUMERATE_END,
},
{
.notify_phase = READY_TO_BOOT,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_FINALIZE,
.timestamp_before = TS_FSP_FINALIZE_START,
.timestamp_after = TS_FSP_FINALIZE_END,
},
{
.notify_phase = END_OF_FIRMWARE,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
.timestamp_before = TS_FSP_END_OF_FIRMWARE_START,
.timestamp_after = TS_FSP_END_OF_FIRMWARE_END,
},
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9505e1d..72a30c51 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -52,9 +52,9 @@
/* Handle all other errors returned by FSP-S APIs */
/* Assume video failure if attempted to initialize graphics */
if (CONFIG(RUN_FSP_GOP) && vbt_get())
- postcode = POST_VIDEO_FAILURE;
+ postcode = POSTCODE_VIDEO_FAILURE;
else
- postcode = POST_HW_INIT_FAILURE; /* else generic */
+ postcode = POSTCODE_HW_INIT_FAILURE; /* else generic */
switch (phases) {
case FSP_SILICON_INIT_API:
@@ -108,7 +108,7 @@
* don't leave it like this as FSP default settings can be bad choices for coreboot.
*/
if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD))
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Invalid FSPS UPD region\n");
else if (hdr->cfg_region_size > sizeof(FSPS_UPD))
printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n");
@@ -133,7 +133,7 @@
fsp_debug_before_silicon_init(silicon_init, supd, upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POSTCODE_FSP_SILICON_INIT);
/* FSP disables the interrupt handler so remove debug exceptions temporarily */
null_breakpoint_disable();
@@ -146,7 +146,7 @@
printk(BIOS_INFO, "FSPS returned %x\n", status);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
- post_code(POST_FSP_SILICON_EXIT);
+ post_code(POSTCODE_FSP_SILICON_EXIT);
if (CONFIG(BMP_LOGO))
bmp_release_logo();
@@ -173,7 +173,7 @@
if (multi_phase_si_init == NULL)
return;
- post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY);
+ post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY);
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
/* Get NumberOfPhases Value */
multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
@@ -200,7 +200,7 @@
fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status);
}
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
- post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT);
+ post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
}
static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 7fa2af4..f912d9a 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -182,7 +182,7 @@
if (upd_signature != expected_signature) {
/* The UPD signatures are non-zero-terminated ASCII stored as a little endian
uint64_t, so this needs some casts. */
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Invalid UPD signature! FSP provided \"%.8s\", expected was \"%.8s\".\n",
(char *)&upd_signature,
(char *)&expected_signature);