tree d7dce3f047ddfac6e2d707949ac9239654fed8b4
parent 8d0e77bbd4145e138ff43951c8543cea2c3dfd50
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1638985388 -0700
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1641487740 +0000

soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function

The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>