This document captures the coreboot development strategy for Intel SoC named Ice lake.
The Ice Lake processor family is the next generation Intel® Core processor family. These processors are built using Intel's 10 nm+ process.
Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
Intel develops initial Firmware code for Ice Lake SoC.
Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
Clone latest coreboot code as below
$ git clone https://review.coreboot.org/coreboot.git
Place blobs (ucode, me.bin and FSP packages) in appropriate locations
Note: Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. After product launch, FSP binary will be available externally as any other program.
Create coreboot .config
CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl
$ make # the image is generated as build/coreboot.rom
Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off