soc/rockchip/rk3399/sdram: Move RL training into a separate function
Move RL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 6a0a150..9dce649 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -783,6 +783,43 @@
return 0;
}
+static int data_training_rl(u32 channel, const struct rk3399_sdram_params *params)
+{
+ u32 rank = params->ch[channel].rank;
+ u32 i, tmp;
+
+ u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
+
+ for (i = 0; i < rank; i++) {
+ select_per_cs_training_index(channel, i);
+ /* PI_80 PI_RDLVL_EN:RW:16:2 */
+ clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
+ /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
+ clrsetbits32(&denali_pi[74], (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24));
+
+ while (1) {
+ /* PI_174 PI_INT_STATUS:RD:8:18 */
+ tmp = read32(&denali_pi[174]) >> 8;
+
+ /*
+ * make sure status obs not report error bit
+ * PHY_46/174/302/430
+ * phy_rdlvl_status_obs_X:16:8
+ */
+ if ((((tmp >> 8) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1)
+ && (((tmp >> 2) & 0x1) == 0x0))
+ break;
+ else if (((tmp >> 2) & 0x1) == 0x1)
+ return -1;
+ }
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ write32((&denali_pi[175]), 0x00003f7c);
+ }
+ clrbits32(&denali_pi[80], 0x3 << 16);
+
+ return 0;
+}
+
static int data_training(u32 channel, const struct rk3399_sdram_params *params,
u32 training_flag)
{
@@ -839,35 +876,11 @@
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
- for (i = 0; i < rank; i++) {
- select_per_cs_training_index(channel, i);
- /* PI_80 PI_RDLVL_EN:RW:16:2 */
- clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
- /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
- clrsetbits32(&denali_pi[74],
- (0x1 << 8) | (0x3 << 24),
- (0x1 << 8) | (i << 24));
-
- while (1) {
- /* PI_174 PI_INT_STATUS:RD:8:18 */
- tmp = read32(&denali_pi[174]) >> 8;
-
- /*
- * make sure status obs not report error bit
- * PHY_46/174/302/430
- * phy_rdlvl_status_obs_X:16:8
- */
- if ((((tmp >> 8) & 0x1) == 0x1) &&
- (((tmp >> 13) & 0x1) == 0x1) &&
- (((tmp >> 2) & 0x1) == 0x0))
- break;
- else if (((tmp >> 2) & 0x1) == 0x1)
- return -1;
- }
- /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
- write32((&denali_pi[175]), 0x00003f7c);
+ ret = data_training_rl(channel, params);
+ if (ret) {
+ printk(BIOS_ERR, "RL training failed\n");
+ return ret;
}
- clrbits32(&denali_pi[80], 0x3 << 16);
}
/* wdq leveling(LPDDR4 support) */