soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index f39200f..350618f 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -44,6 +44,5 @@
#define BIOSRAM_DATA 0xcd5
#define AB_INDX 0xcd8
#define AB_DATA (AB_INDX+4)
-#define SYS_RESET 0xcf9
#endif /* AMD_STONEYRIDGE_IOMAP_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index c627f7e..f963fdf 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -207,11 +207,6 @@
#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
-/* IO 0xcf9 - Reset control port*/
-#define FULL_RST BIT(3)
-#define RST_CMD BIT(2)
-#define SYS_RST BIT(1)
-
typedef struct aoac_devs {
unsigned int :5;
unsigned int ic0e:1; /* 5: I2C0 */
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 88050a6..d609205 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
+#include <cf9_reset.h>
#include <reset.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
@@ -40,7 +41,7 @@
/* De-assert and then assert all PwrGood signals on CF9 reset. */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
TOGGLE_ALL_PWR_GOOD);
- outb(RST_CMD | SYS_RST, SYS_RESET);
+ outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_warm_reset(void)
@@ -49,7 +50,7 @@
clear_bios_reset();
/* Assert reset signals only. */
- outb(RST_CMD | SYS_RST, SYS_RESET);
+ outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_board_reset(void)